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4 - channel, 4.8 khz , ultralow noise , 24 - bit sigma - delta adc with pga data sheet AD7193 rev. d document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. t el: 781.329.4700 ? 2009 C 2013 analog devices, inc. all rights reserved. technical support www.analog.com features fast settling filter option 4 differential/8 pseudo differential input channels rms n oise: 1 1 nv @ 4.7 hz (gain = 128) 15.5 noise - free bits @ 2.4 khz (gain = 128) up to 22 noise - free bits (gain = 1) offset drift: 5 nv/c gain drift: 1 ppm/c spe cified drift over time automatic channel sequencer programmable gain (1 to 128) output data rate: 4.7 hz to 4.8 khz internal or external clock simultaneous 50 hz/60 hz rejection 4 general - purpose digital outputs power supply av dd : 3 v to 5.25 v dv dd : 2.7 v to 5.25 v current: 4 . 6 5 ma temperature range : ? 40c to +105c 28- lead tssop and 32 - lead lfcsp p ackage s interface 3 - wire serial spi, qspi?, microwire?, and dsp compatible schmitt trigger on sclk applications plc/dcs analog input modules data acquisition st rain ga ge transducers pressure measurement temperature measurement flow measurement weigh scales chromatography medical and scientific instrumentation general description the ad719 3 is a low noise, complete analog front end for high precision measurement a pplications. it contains a low noise, 24- bit sigma - delta ( - ) analog - to - digital converter ( adc ) . the on - chip low noise gain stage means that signals of small amplitude can interface directly to the adc. the device can be configured to have four differential inputs or eight pseudo differential inputs. the on - ch ip channel sequencer allows several channels to be enabled simultaneously , and the ad719 3 sequentially convert s on each enabled channel, simplifying communication with the part. the on - chip 4.92 mhz clock can be used as the clock source to the adc or, alte rnatively, an external clock or crystal can be used. the output data rate from the part can be varied from 4.7 hz to 4.8 khz. the device has a very flexible digital filter, including a fast settling option . variables such as output data rate and settling time are dependent on the option selected . the AD7193 also includes a zero latency option . the part operates with a power supply from 3 v to 5.25 v. it consumes a current of 4 .6 5 ma , and i t is available in a 28- lead tssop package and a 32 - lead lfcsp packa ge . functional block dia gram mclk1 mclk2 p0/refin2(?) p1/refin2(+) dv dd dgnd refin1(+) refin1(?) ain1 ain2 ain3 ain4 aincom bpdsw agnd AD7193 serial interface and control logic temp sensor clock circuitry dout/rdy din sclk cs sync p3 p2 av dd agnd ain5 ain6 ain7 ain8 - adc pga mux 08367-001 figure 1.
important links for the AD7193 * last content update 12/19/2013 07:06 pm documentation ug-517 (AD7193 key sheet) a 6-page, concise, clear and downloadable brief on the AD7193 an-1131: chopping on the ad7190, ad7192, AD7193, ad7194, and ad7195 an-1084: channel switching: ad7190, ad7192, AD7193, ad7194, ad7195 an-1069: zero latency for the ad7190, ad7192, AD7193, ad7194, and ad7195 cn-0287: fully isolated 4-channel, temperature measurement circuit optimized for performance, robustness, and low cost cn-0209: fully programmable universal analog front end for process control applications tutorial on technical and performance benefits of ad719x family ug-223: evaluation board for the AD7193, 4.8 khz, ultralow noise, 24-bit sigma-delta adc ms-2210: designing power supplies for high speed adc high-resolution adcs an overview industrial ics solutions bulletin faqs for the ad719x family. evaluation kits & symbols & footprints view the evaluation boards and kits page for documentation and purchasing symbols and footprints design support submit your support request here: linear and data converters embedded processing and dsp telephone our customer interaction centers toll free: americas: 1-800-262-5643 europe: 00800-266-822-82 china: 4006-100-006 india: 1800-419-0108 russia: 8-800-555-45-90 quality and reliability lead(pb)-free data sample & buy AD7193 view price & packaging; request evaluation board request samples check inventory & purchase find local distributors similar products & parametric selection tables find similar products by operating parameters product recommendations & reference designs cn-0287 : isolated 4-channel, thermocouple/rtd temperature measurement system with 0.5 o c accuracy cn-0209 : fully programmable universal analog front end for process control applications design tools, models, drivers & software digital filter model spreadsheets bemicro fpga project for cn0209 with nios driver cn0209 fmc-sdp interposer & evaluation board / xilinx kc705 reference design AD7193 pmod xilinx fpga reference design AD7193 - no-os driver for renesas microcontroller platforms AD7193 - no-os driver for microchip microcontroller platforms design collaboration community collaborate online with the adi support team and other designers about select adi products. suggested companion products recommended driver amplifier for the AD7193 for a low noise, low distortion, rail-to-rail output, differential driver, we recommend the ada4940-1 . for a precision, general purpose, rail-to-rail, single-ended input, we recommend the ad8628 . recommended precision reference for the AD7193 for low noise, high accuracy, 2.5v reference, we recommend the adr421 or the adr431 . for low noise, high accuracy, 5v reference, we recommend the adr425 . recommended digital isolators for the AD7193 for a low cost standard digital isolator, we recommend the adum1411 or the adum1412 . for a digital isolator with isopower, we recommend the adum5401 or the adum5402 . * this page was dynamically generated by analog devices, inc. and inserted into this data sheet. note: dynamic changes to the content on this page (labeled 'important links') does not constitute a change to the revision number of the product data sheet. this content may be frequently modified. powered by tcpdf (www.tcpdf.org)
AD7193 data sheet rev. d | page 2 of 56 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 3 specifications ..................................................................................... 4 timing characteristics ................................................................ 8 absolute maximum ratings .......................................................... 10 thermal resistance .................................................................... 10 esd caution ................................................................................ 10 pin configurations and function descrip tions ......................... 11 typical performance characteristics ........................................... 15 rms noise and resolution ............................................................ 18 sinc 4 chop disabled ................................................................... 18 sinc 3 chop disabled ................................................................... 19 fast settling ................................................................................. 20 on - chip registers .......................................................................... 21 communications register ......................................................... 22 status register ............................................................................. 23 mode register ............................................................................. 24 configuration register .............................................................. 27 data register ............................................................................... 29 id register ................................................................................... 29 gpocon register ..................................................................... 29 offset register ............................................................................. 30 f ull - scale register ...................................................................... 30 adc circuit information .............................................................. 31 overview ...................................................................................... 31 ana log input channel ............................................................... 32 programmable gain array (pga) ........................................... 32 reference ..................................................................................... 32 reference detect ......................................................................... 33 bipolar/unipolar configuration .............................................. 33 data output coding .................................................................. 33 burnout currents ....................................................................... 33 channel sequencer .................................................................... 33 digital interface .......................................................................... 34 reset ............................................................................................. 38 system synchronization ............................................................ 38 enable parity ............................................................................... 38 clock ............................................................................................ 38 bridge power - down switch ...................................................... 38 temperature sensor ................................................................... 39 logi c outputs ............................................................................. 39 calibration ................................................................................... 39 digital filter .................................................................................... 41 sinc 4 filter (chop disabled) ..................................................... 41 sinc 3 filter (chop disabled) ..................................................... 43 chop enabled (sinc 4 filter) ...................................................... 45 chop enabled (sinc 3 filter) ...................................................... 47 fast settling mode (sinc 4 filter) ............................................... 48 fast settling mode (sinc 3 filter) ............................................... 50 fast settling mode (chop enabled) ......................................... 51 summary of filter options ....................................................... 52 groundin g and layout .................................................................. 53 applications information .............................................................. 54 flowmeter .................................................................................... 54 outline dimensions ....................................................................... 55 ordering guide .......................................................................... 55
data sheet AD7193 rev. d | page 3 of 56 revision history 3 /1 3 rev. c to rev. d changes to con2 to con0 description; table 22 .................... 28 changes to equations in data output coding section ............. 33 12/11 rev. b to rev. c moved revision history section ..................................................... 3 changes to table 6 .......................................................................... 13 4 / 10 rev. a to rev. b added 32- lead lfcsp ...................................................... universal changes to table 7 .......................................................................... 17 changes to communications register, table 16 ......................... 20 updated outline dimensions ........................................................ 5 4 changes to ordering guide ........................................................... 5 4 9/09 rev. 0 to rev. a changes to internal/external clock, internal clock frequency parameter, table 1 ............................................................................. 5 changes to figure 7 and figure 8 ................................................. 1 4 changes to table 6 .......................................................................... 1 7 changes to table 9 .......................................................................... 1 8 changes to table 12, table 13, and table 14 ............................... 1 9 chan ges to table 19 ........................................................................ 2 4 changes to table 22 and table 23 ................................................. 2 7 changes to offset register and full - scale register section s .... 2 9 changes to reference section ....................................................... 31 changes to data output coding section .................................... 3 2 changes to sinc 4 50 hz/60 hz rejection sectio n ....................... 41 changes to sinc 3 50 hz/60 hz rejection section ....................... 4 3 changes to 50 hz/60 hz rejection, sinc 4 filter section ............ 4 7 changes to summary of filter options section and table 35 .. 5 2 7/09 revision 0: initial version
AD7193 data sheet rev. d | page 4 of 56 specifications av dd = 3 v to 5.25 v , dv dd = 2.7 v to 5.25 v , a gnd = dgnd = 0 v; refin x (+) = 2.5 v or av dd , refinx ( ? ) = a gnd , mclk = 4.9 2 mhz , t a = t min to t max , unless otherwise noted. table 1 . parameter min typ max unit test conditions/comments 1 adc output data rate 4.7 4800 hz chop disabled 1.17 1200 hz chop enabled, sinc 4 filter 1.56 1600 hz chop enabled, sinc 3 filter no missing codes 2 24 bits fs [9:0] 3 > 1, sinc 4 filter 24 bits fs [9:0] 3 > 4, sinc 3 filter resolution see the rms noise and resolution section rms noise and output data rates see the rms noise and resolution section integral nonlinearity gain = 1 2 2 10 ppm of fsr av dd = 5 v 2 15 ppm of fsr av dd = 3 v gain > 1 5 30 ppm of fsr av dd = 5 v 1 5 30 ppm of fsr av dd = 3 v offset error 4 , 5 150/gain v chop disabled 1 v chop enabled , av dd = 5 v 0.5 v chop enabled, av dd = 3 v offset error drift vs. temperature 150/gain nv/c gain = 1 to 16; chop disabled 5 nv/c gain = 32 to 128; chop disabled 5 nv/c chop enabled offset error drift vs. time 25 nv/1000 hour s gain > 32 gain error 4 0.001 % av dd = 5 v, gain = 1, t a = 25c (factory calibration conditions) ?0.39 % gain = 128, before full - scale calibration (see table 27 ) 0.003 % gain > 1, after internal full - scale calibration, av dd 4.75 v 0.005 % gain > 1, after internal full - scale calibration, av dd < 4.75 v gain drift vs. temperature 1 ppm/c gain drift vs. time 10 ppm/ 1000 hours gain = 1 power supply rejection 90 db gain = 1, v in = 1 v 95 110 db gain > 1, v in = 1 v/gain common - mode rejection @ dc 110 db gain = 1, v in = 1 v @ dc 1 05 db gain > 1, v in = 1 v/gain @ 50 hz, 60 hz 2 120 db 10 hz output data r ate, 50 hz 1 hz, 60 hz 1 hz @ 50 hz 2 120 db 50 hz output data rate, 50 hz 1 hz @ 60 hz 2 120 db 60 hz output data rate, 60 hz 1 hz @ 50 hz 2 115 db fast settling , fs [9:0] 3 = 6, a verage by 16, 50 hz 1 hz @ 60 hz 2 115 db fast settling, fs [9:0] 3 = 5, a verage by 16, 6 0 hz 1 hz
data sheet AD7193 rev. d | page 5 of 56 parameter min typ max unit test conditions/comments 1 normal - mode rejection 2 sinc 4 filter internal clock @ 50 hz, 60 hz 100 db 10 hz output data rate, 50 hz 1 hz, 60 hz 1 hz 74 db 50 hz output data rate, rej60 6 = 1, 50 hz 1 hz, 60 hz 1 hz @ 50 hz 96 db 50 hz output data rate, 50 hz 1 hz @ 60 hz 97 db 60 hz output data rate, 60 hz 1 hz external clock @ 50 hz, 60 hz 120 db 10 hz output data rate, 50 hz 1 hz, 60 hz 1 hz 82 db 50 hz output data rate, rej60 6 = 1, 50 hz 1 hz, 60 hz 1 hz @ 50 hz 120 db 50 hz output data rate, 50 hz 1 hz @ 60 hz 120 db 60 hz output data rate, 60 hz 1 hz sinc 3 filter internal clock @ 50 hz, 60 hz 75 db 10 hz output data rate, 50 hz 1 hz, 60 hz 1 hz 60 db 50 hz output data rate, rej60 6 = 1, 50 hz 1 hz, 60 hz 1 hz @ 50 hz 70 db 50 hz output data rate, 50 hz 1 hz @ 60 hz 70 db 60 hz output data rate, 60 hz 1 hz external clock @ 50 hz, 60 hz 100 db 10 hz output data rate, 50 hz 1 hz, 60 hz 1 hz @ 50 hz 67 db 50 hz output data ra te, rej60 6 = 1, 50 hz 1 hz, 60 hz 1 hz @ 50 hz 95 db 50 hz output data rate, 50 hz 1 hz @ 60 hz 95 db 60 hz output data rate, 60 hz 1 hz fast settling internal clock @ 50 hz 26 db fs[9:0] 3 = 6, a verage by 16, 50 hz 0.5 hz @ 60 hz 26 db fs[9:0] 3 = 5, a verage by 16, 60 hz 0.5 hz external clock @ 50 hz 40 db fs[9:0] 3 = 6, a verage by 16, 50 hz 0.5 hz @ 60 hz 40 db fs[9:0] 3 = 5, a verage by 16, 60 hz 0.5 hz analog inputs differential input voltage ranges v ref /gain v v ref = refinx(+) ? refinx(?), gain = 1 to 128 ?(av dd ? 1.25 v)/gain +(av dd ? 1.25 v)/gain v gain > 1 absolute ain voltage limits 2 unbuffered mode agnd ? 0.05 av dd + 0.05 v buffered mode agnd + 0.25 av dd ? 0.25 v analog input cu rrent buffered mode input current 2 ?2 +2 na gain = 1 ?3 +3 na gain > 1 input current drift 5 pa/c unbuffered mode input current 3.5 a/v gain = 1, input current varies with input voltage 1 a/v gain > 1 input current drift 0.05 na/v/c external clock 1.6 na/v/c internal clock
AD7193 data sheet rev. d | page 6 of 56 parameter min typ max unit test conditions/comments 1 reference input refin voltage 1 av dd v refin = refinx(+) ? refinx(?), the differential input must be limited to (av dd ? 1.25 v)/gain when gain > 1 absolute refin voltage limits 2 a gnd ? 0.05 av dd + 0.05 v average reference input current 4.5 a/v average reference input current drift 0.03 na/v/c external clock 1.3 na/v/c internal clock normal mode rejection 2 same as for analog inputs common - mode rejection 100 db reference detect levels 0.3 0.6 v temperature sensor accuracy 2 c applies after user calibration at 25c sensitivity 2815 codes/c bipolar mode bridge power - down switch r on 10 allowable current 2 30 ma continuous current burnout currents ain current 500 na analog inputs must be buffered and chop disabled digital outputs (p0 to p3) output high voltage, v oh av dd ? 0.6 v av dd = 3 v, i source = 100 a 4 v av dd = 5 v, i source = 200 a output low voltage, v ol 0.4 v av dd = 3 v, i sink = 100 a 0.4 v av dd = 5 v, i sink = 800 a floating - state leakage current 2 ?100 +100 na floating - state output capacitance 10 pf internal/external clock internal clock frequency 4.72 4.92 5.12 mhz duty cycle 50:50 % external clock/crystal frequency 2.4576 4.9152 5.12 mhz input low voltage, v inl 0.8 v dv dd = 5 v 0.4 v dv dd = 3 v input high voltage, v inh 2.5 v dv dd = 3 v 3.5 v dv dd = 5 v input current ?10 +10 a logic inputs input high voltage, v inh 2 2 v input low vol tage, v inl 2 0.8 v hysteresis 2 0.1 0.25 v input currents ?10 +10 a logic output (dout / rdy ) output high voltage, v oh 2 dv dd ? 0.6 v dv dd = 3 v, i source = 100 a 4 v dv dd = 5 v, i source = 200 a output low voltage, v ol 2 0.4 v dv dd = 3 v, i sink = 100 a 0.4 v dv dd = 5 v, i sink = 1.6 ma floating - state leakage current ?10 +10 a floating - state output capacitance 10 pf
data sheet AD7193 rev. d | page 7 of 56 parameter min typ max unit test conditions/comments 1 data output coding offset binary system calibration 2 full - scale calibratio n limit 1.05 fs v zero - scale calibration limit ?1.05 fs v input span 0.8 fs 2.1 fs v power requirements 7 power supply voltage av dd ? agnd 3 5.25 v dv dd ? dgnd 2.7 5.25 v power supply currents ai dd current 0.85 1 ma gain = 1, buffer off 1 1.25 ma gain = 1, buffer on 2.8 3.6 ma gain = 8, buffer off 3.2 3.9 ma gain = 8, buffer on 3.8 4.7 ma gain = 16 to 128, buffer off 4.3 5.3 ma gain = 16 to 128, buffer on di dd current 0.35 0.4 ma dv dd = 3 v 0.5 0.6 ma dv dd = 5 v 1.5 ma external crystal used i dd 3 a power - down mode 1 temperature r ange : ?40c to +10 5c. 2 spe cification is not production tested but is supported by characterization data at initial product release. 3 fs[9:0] is the decimal equivalent of bit fs9 to bit fs0 in the mode register. 4 following a system or internal zero - scale calibration, the offset er ror is in the order of the noise for the programmed gain and output data rate selected. a system full - scale calibration reduces the gain error to the order of the noise for the programmed gain and output data rate. 5 the analog inputs are configured for di fferential mode. 6 rej60 is a bit in the mode register. when the first notch of the sinc filter is at 50 hz, a notch is placed at 60 hz when rej 60 is set to 1. this gives simultaneous 50 hz/60 hz rejection. 7 digital inputs equal to dv dd or dgnd.
AD7193 data sheet rev. d | page 8 of 56 timing characteristi cs av dd = 3 v to 5.25 v, dv dd = 2.7 v to 5.25 v, agnd = dgnd = 0 v, input logic 0 = 0 v, input logic 1 = dv dd , unless otherwise noted. table 2 . parameter limit at t min , t max (b version) unit conditions/comments 1 , 2 read and write operations t 3 100 ns min sclk high pulse width t 4 100 ns min sclk low pulse width read operation t 1 0 ns min cs falling edge to dout/ rdy active time 60 ns max dv dd = 4.75 v to 5.25 v 80 ns max dv dd = 2.7 v to 3.6 v t 2 3 0 ns min sclk active edge to data valid delay 4 60 ns max dv dd = 4.75 v to 5.25 v 80 ns max dv dd = 2.7 v to 3.6 v t 5 5 , 6 10 ns min bus relinquish time after cs inactive edge 80 ns max t 6 0 ns min sclk inactive edge to cs inactive edge t 7 10 ns min sclk inactive edge to dout/ rdy high write operation t 8 0 ns min cs falling edge to sclk active edge setup time 4 t 9 30 ns min data valid to sclk edge setup time t 10 25 ns min data valid to sclk edge hold time t 11 0 ns min cs rising edge to sclk edge hold time 1 s ample tested during initial release to ensure compliance. all input signals are specified with t r = t f = 5 ns (10% to 90% of dv dd ) and timed from a voltage level of 1.6 v. 2 see figure 3 and figure 4 . 3 these numbers are measured with the load cir cuit shown in figure 2 and defined as the time required for the output to cross the v ol or v oh limits. 4 the sclk active edge is the falling edge of sclk. 5 these numbers are derived from the measured time taken by the data output to change 0.5 v when loaded with the circuit shown in figure 2 . the measured number is then extrapolated back to remove the effects of charging or discharging the 50 pf capacitor. this means that the times quoted in the timing characteristics are the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances. 6 rdy retu rns high after a read of the data register . i n single conversion mode and continuous conversion mode, the same data can be read again, if required, while rdy is high, although care should be taken to ensure that subsequent reads do not occur clo se to the next output update. if the continuous read feature is enabled , the digital word can be read only once. circuit and timing diagrams i sink (1.6ma with dv dd = 5v, 100a with dv dd = 3v) i source (200a with dv dd = 5v, 100a with dv dd = 3v) 1.6v to output pin 50pf 08367-002 figure 2 . load circuit for timing characterization
data sheet AD7193 rev. d | page 9 of 56 t 2 t 3 t 4 t 1 t 6 t 5 t 7 cs (i) dout/rdy (o) sclk (i) i = input, o = output msb lsb 0 8367-003 figure 3. read cycle timing diagram i = input, o = output cs (i) s clk (i) din (i) msb lsb t 8 t 9 t 10 t 11 0 8367-004 figure 4. write cycle timing diagram
AD7193 data sheet rev. d | page 10 of 56 absolute maximum ratings t a = 25c, unless otherwise noted. table 3. parameter rating av dd to agnd ?0.3 v to +6.5 v dv dd to agnd ?0.3 v to +6.5 v agnd to dgnd ?0.3 v to +0.3 v analog input voltage to agnd ?0.3 v to av dd + 0.3 v reference input voltage to agnd ?0.3 v to av dd + 0.3 v digital input voltage to dgnd ?0.3 v to dv dd + 0.3 v digital output voltage to dgnd ?0.3 v to dv dd + 0.3 v ainx/digital input current 10 ma operating temperature range ?40c to +105c storage temperature range ?65c to +150c maximum junction temperature 150c lead temperature, soldering reflow 260c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for the surface-mount packages. table 4. thermal resistance package type ja jc unit 28-lead tssop 97.9 14 c/w 32-lead lfcsp 32.5 32.71 c/w esd caution
data sheet AD7193 rev. d | page 11 of 56 pin configuration s and function descrip tions nc = no connect 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 mclk2 sclk cs p1/refin2(+) p2 p3 mclk1 dout/rdy sync dv dd agnd dgnd av dd p0/refin2(?) nc aincom ain4 ain2 ain1 bpdsw refin1(?) refin1(+) ain5 ain3 ain6 ain7 ain8 din AD7193 t o p view (not to scale) 08367-005 figure 5. 28 - lead tssop pin configuration table 5 . 28 - lead tssop pin function descriptions pin no. mnemonic description 1 mclk1 when the master clock for the device is provided externally by a crystal, the crystal is connected between mclk1 and mclk2. 2 mclk2 master clock signal for the d evice. the AD7193 h as an internal 4.92 mhz clock. this internal clock can be made avai lable on the mclk2 pin. the clock for the AD7193 can also be provided externally in the form of a crystal or external clock. a crystal can be tied across the mclk1 and mclk2 pins. alternatively, the mclk2 pin can be driven with a cmos - compatible clock and with the mclk1 pin remaining unconnected. 3 sclk serial clock input. this serial clock input is for data transfers to and from the adc. the sclk has a schmitt - triggered input, making the interface suitable for opto - isolated applications. the serial cloc k can be continuous with all data transmitted in a continuous train of pulses. alternatively, it can be a noncontinuous c lock with the information transmitted to or from the adc in smaller batches of data. 4 cs chip select input. t his is an active low logic input used to select the adc. cs can be used to select the adc in systems with more than one device on the serial bus or as a frame synchronization signal in communicating with the device. cs can be hardwired low, allowing the adc to operate in 3 - wire mode with sclk, din, and dout used to interface with the device. 5 p3 digital output pin. this pin can function as a general - purpose output bit referenced between av dd and agnd. 6 p2 d igital output pin. this pin can function as a general - purpose output bit referenced between av dd and agnd. 7 p1/refin2(+) digital output pin/positive reference input. this pin functions as a general - purpose output bit referenced between av dd and agnd. whe n the refsel bit in the configuration register = 1, this pin functions as refin2(+). an external reference can be applied between refin2(+) and refin2(?). refin2(+) can lie anywhere between av dd and a gnd + 1 v. the nominal reference voltage, (refin2(+) ? r efin2(?)), is av dd , but the part functions with a reference from 1 v to av dd . 8 p0/refin2( ? ) digital output pin/negative reference input. this pin functions as a general - purpose output bit referenced between av dd and agnd. when the refsel bit in the confi guration register = 1, this pin functions as refin2( ? ). this reference input can lie anywhere between a gnd and av dd ? 1 v. 9 nc no connect. tie t his pin to agnd. 10 aincom analog i nput ain1 to analog input ain 8 are referenced to this i nput when configur ed for pseudo differential operation. 11 ain1 analog input. this pin can be configured as the positive input of a fully differential input pair when used with ain2 or as a ps eudo differential input when used with aincom. 12 ain2 analog input. this pin c an be configured as the negative input of a fully differential input pair when used with ain1 or as a pseudo differential input when used with aincom. 13 ain3 analog input. this pin can be configured as the positive input of a fully differential input pai r when used with ain4 or as a pseudo differential input when used with aincom.
AD7193 data sheet rev. d | page 12 of 56 pin no. mnemonic description 14 ain4 analog input. this pin can be configured as the negative input of a fully differential input pair when used with ain3 or as a pseudo differential input when used with a incom. 15 ain5 analog input. this pin can be configured as the positive input of a fully differential input pair when used with ain6 or as a pseudo differential input when used with aincom. 16 ain6 analog input. this pin can be configured as the negative input of a fully differential input pair when used with ain 5 or as a pseudo differential input when used with aincom. 17 ain7 analog input. this pin can be configured as the positive input of a fully differential input pair when used with ain8 or as a ps eudo differential input when used with aincom. 18 ain8 analog input. this pin can be configured as the negative input of a fully differential input pair when used with ain7 or as a pseudo differential input when used with aincom. 1 9 refin1(+) positive r eference input. an external reference can be applied between refin1(+) and refin1(?). refin1(+) can lie anywhere between av dd and agnd + 1 v. the nominal reference voltage, (refin1(+) ? refin1(?)), is av dd , but the part functions with a reference from 1 v to av dd . 20 refin1(?) negative reference input. this reference input can lie anywhere between agnd and av dd ? 1 v. 21 bpdsw bridge power - down switch to agnd. 22 agnd analog ground reference point. 23 dgnd digital ground reference point. 24 av dd ana log supply voltage, 3 v to 5.25 v. av dd is independent of dv dd . therefore, dv dd can be operated at 3 v with av dd at 5 v or vice versa. 25 dv dd digital supply voltage, 2.7 v to 5.25 v. dv dd is independent of av dd . therefore, av dd can be operated at 3 v wit h dv dd at 5 v or vice versa. 26 sync logic input that allows for synchronization of the digital filters and analog modulators when using a number of AD7193 devices. while sync is low, the nodes of the digital filter, the filter control logic, and the calibration control logic are reset, and the analog modulator is also held in its reset state. sync does not affect the digital interface but does reset rdy to a high s tate if it is low. sync has a pull - up resistor internally to dv dd . 27 dout/ rdy serial data output/data ready output. dout/ rdy serves a dual purpose. it functions as a serial data output pin to access the output shift register of the adc. the output shift register can contain data from any of the on - chip data or control registers. in addition, dout/ rdy operates as a data ready pin, going low to indicate the completio n of a conversion. if the data is not read after the conversion, the pin goes high before the next update occurs. the dout/ rdy falling edge can be used as an interrupt to a processor, indicating that valid data is available. with an external serial clock, the data can be read using the dout/ rdy pin. with cs low, the data - /control - word information is placed on the dout/ rdy pin on the sclk falling edge and is valid on the sclk rising edge. 2 8 din serial data input to the input shift register on the adc. data in this shift register is transferred to the control registers in the adc, with the register selection bits of the communications register identifying the approp riate register.
data sheet AD7193 rev. d | page 13 of 56 08367-065 notes 1. nc = no connect. 2. connect exposed pad to agnd. 24 dv dd 23 av dd 22 dgnd 21 agnd 20 bpdsw 19 nc 18 refin1(?) 17 refin1(+) 1 2 3 4 5 6 7 8 p3 p2 p1/refin2(+) p0/refin2(?) nc nc nc aincom 9 10 11 12 13 14 15 16 ain1 ain2 ain3 ain4 ain5 ain6 ain7 ain8 32 31 30 29 28 27 26 25 cs sclk mclk2 mclk1 din dout/rdy nc sync top view (not to scale) AD7193 figure 6. 32-lead lfcsp pin configuration table 6. 32-lead lfcsp pin function descriptions pin no. mnemonic description 1 p3 digital output pin. this pin can function as a general-purpose output bit referenced between av dd and agnd. 2 p2 digital output pin. this pin can function as a general-purpose output bit referenced between av dd and agnd. 3 p1/refin2(+) digital output pin/positive reference input. this pin functions as a general-purp ose output bit referenced between av dd and agnd. when the refsel bit in the configuration register = 1, this pin functions as refin2(+). an external reference can be applied between refin2(+) and refin2(?). refin2(+) can lie anywhere between av dd and agnd + 1 v. the nominal reference voltage, (refin2(+) ? refin2(?)), is av dd , but the part functions with a reference from 1 v to av dd . 4 p0/refin2(?) digital output pin/negative reference input. this pin functions as a general-purpose output bit referenced between av dd and agnd. when the refsel bit in the configuration register = 1, this pin functions as refin2(?). this reference input can lie anywhere between agnd and av dd ? 1 v. 5, 6, 7, 19, 26 nc no connect. tie these pins to agnd. 8 aincom analog input ain1 to analog input ain8 are referenced to this input when configured for pseudo differential operation. 9 ain1 analog input. this pin can be configured as the positive input of a fully differential input pair when used with ain2 or as a pseudo differential input when used with aincom. 10 ain2 analog input. this pin can be config ured as the negative input of a fully differential input pair when used with ain1 or as a pseudo differen tial input when used with aincom. 11 ain3 analog input. this pin can be configured as the positive input of a fully differential input pair when used with ain4 or as a pseudo differential input when used with aincom. 12 ain4 analog input. this pin can be config ured as the negative input of a fully differential input pair when used with ain3 or as a pseudo differen tial input when used with aincom. 13 ain5 analog input. this pin can be configured as the positive input of a fully differential input pair when used with ain6 or as a pseudo differential input when used with aincom. 14 ain6 analog input. this pin can be config ured as the negative input of a fully differential input pair when used with ain5 or as a pseudo differen tial input when used with aincom. 15 ain7 analog input. this pin can be configured as the positive input of a fully differential input pair when used with ain8 or as a pseudo differential input when used with aincom. 16 ain8 analog input. this pin can be config ured as the negative input of a fully differential input pair when used with ain7 or as a pseudo differen tial input when used with aincom. 17 refin1(+) positive reference input. an external reference can be applied between refin1(+) and refin1(?). refin1(+) can lie anywhere between av dd and agnd + 1 v. the nominal reference voltage, (refin1(+) ? refin1(?)), is av dd , but the part functions with a reference from 1 v to av dd . 18 refin1(?) negative reference input. this reference input can lie anywhere between agnd and av dd ? 1 v. 20 bpdsw bridge power-down switch to agnd.
AD7193 data sheet rev. d | page 14 of 56 pin no. mnemonic description 21 agnd analog groun d reference point. 22 dgnd digital ground reference point. 23 av dd analog supply voltage, 3 v to 5.25 v. av dd is independent of dv dd . therefore, dv dd can be operated at 3 v with av dd at 5 v or vice versa. 24 dv dd digital supply voltage, 2.7 v to 5.25 v. dv dd is independent of av dd . therefore, av dd can be operated at 3 v with dv dd at 5 v or vice versa. 25 sync logic input that allows for synchronization of the digital filters and analog modulators when using a number of AD7193 devi ces. while sync is low, the nodes of the digital filter, the filter control logic, and the calibration control logic are reset, and the analog modulator is also held in its reset state. sync does not affect the digital interface but does reset rdy to a high state if it is low. sync has a pull - up resistor internally to dv dd . 27 dout/ rdy serial data output/data ready output. dout/ rdy serves a dual purpose. it functions as a serial data output pin to access the output shift register of the adc. the output shift register can contain data from any of the on - chip data or control registers. in addition, dout/ rdy operates as a data ready pin, going low to indicate the completion of a conversion. if the data is not read after the conversion, the pin goes high before the next update occurs. the dout/ rdy falling edge can be used as an int errupt to a processor, indicating that valid data is available. with an external serial clock, the data can be read using the dout/ rdy pin. with cs low, the data - /control - word information is placed on the dout/ rdy pin on the sclk falling edge and is valid on the sclk rising edge. 28 din serial data input to the input shift register on the adc. data in this shift register is transferred to the control registers in the adc, with the regis ter selection bits of the communications register identifying the appropriate register. 29 mclk1 when the master clock for the device is provided externally by a crystal, the crystal is connected between mclk1 and mclk2. 30 mclk2 master clock signal fo r the device. the AD7193 has an internal 4.92 mhz clock. this internal clock can be made available on the mclk2 pin. the clock for the AD7193 can also be provided externally in the form of a crystal or external clock. a crystal can be tied across the mclk1 and mclk2 pins. alternatively, the mclk2 pin can be driven with a cmos - compatible clock and with the mclk1 pin remaining unconnected. 31 sclk serial clock input. this serial clock input is for data transfers to and from the adc. the sclk has a schmitt - triggered input, making the interface suitable for opto - isolated applications. the serial clock can be continuous with all data transmitted in a continuous train of pulses. alternatively, it can be a noncontinuous clock with the information transmitted to or from the adc in smaller batches of data. 32 cs chip select input. this is an active low logic input used to select the adc. cs can be used to select the adc in systems with more than one device on the seri al bus or as a frame synchronization signal in communicating with the device. cs can be hardwired low, allowing the adc to operate in 3 - wire mode with sclk, din, and dout used to interface with the device. epad the exposed pad mus t be connected to agnd.
data sheet AD7193 rev. d | page 15 of 56 typical performance characteristics 08367-006 0 200 400 600 800 1000 sample code 8,387,468 8,387,470 8,387,472 8,387,474 8,387,476 8,387,478 8,387,480 8,387,482 8,387,484 8,387,486 figure 7 . noise (v ref = av dd = 5 v, output data rate = 4.7 hz, gain = 128, chop disabled, sinc 4 filter) 08367-007 0 50 100 150 200 8,387,470 8,387,472 8,387,474 8,387,476 8,387,478 8,387,480 8,387,482 8,387,484 code occurrence figure 8 . noise distribution hi stogram (v ref = av dd = 5 v, output data rate = 4.7 hz, gain = 128, chop disabled, sinc 4 filter) 08367-008 8,388,830 8,388,840 8,388,850 8,388,860 8,388,870 8,388,880 8,388,890 8,388,900 8,388,910 8,388,920 0 200 400 600 800 1000 sample code figure 9 . noise (v ref = av dd = 5 v, output data rate = 2400 hz, gain = 1, chop disabled, sinc 4 filter) 08367-009 0 10 20 30 40 50 8,388,830 8,388,860 8,388,890 8,388,920 code occurrence figure 10 . noise distribution histogram (v ref = av dd = 5 v, output data rate = 2400 hz, gain = 1, chop disabled, sinc 4 filter) 08367-010 8,388,864 8,388,866 8,388,868 8,388,870 8,388,872 8,388,874 8,388,876 8,388,878 8,388,880 0 200 400 600 800 1000 sample code figure 11 . noise (v ref = av dd = 5 v, output data rate = 42.1 hz (fs[9:0] = 6, average by 16), ga in = 1, chop disabled, sinc 4 filter) 08367-011 0 50 100 150 200 8,388,864 8,388,868 8,388,872 8,388,876 8,388,880 code occurrence figure 12 . noise distribution histogram (v ref = av dd = 5 v, output data rate = 42.1 hz (fs[9:0] = 6, average by 16), gain = 1, chop disabled, sinc 4 filter)
AD7193 data sheet rev. d | page 16 of 56 5 ?2 ?1 0 1 2 3 4 ?4 ?3 ?2 ?1 0 1 2 3 4 inl (ppm of fsr) v in (v) 08367-012 figure 13 . inl (gain = 1) 20 ?20 ?15 ?10 ?5 0 5 10 15 ?0.03 ?0.02 ?0.01 0 0.01 0.02 0.03 inl (ppm of fsr) v in (v) 08367-013 figure 14 . inl (gain = 128) 170 168 166 164 162 160 156 158 154 ?60 ?40 ?20 0 20 40 60 80 100 120 offset (v) temperature (c) 08367-014 figure 15 . offset vs . temperature (gain = 1, chop disabled) 0.4 ?1.4 ?1.2 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 ?60 ?40 ?20 0 20 40 60 80 100 120 offset (v) temperature (c) 08367-015 figure 16 . offset vs . temperature (gain = 128, chop disable d) ?60 ?40 ?20 0 20 40 60 80 100 120 gain temperature (c) 08367-016 0.999988 0.999990 0.999992 0.999994 0.999996 0.999998 1.000000 1.000002 1.000004 1.000006 1.000008 figure 17 . gain vs . temperature (gain = 1) ?60 ?40 ?20 0 20 40 60 80 100 120 gain temperature (c) 08367-017 127.988 127.990 127.992 127.994 127.996 127.998 128.000 128.002 128.004 figure 18 . gain vs . temperature (gain = 128)
data sheet AD7193 rev. d | page 17 of 56 08367-018 14 16 18 20 22 24 1 10 100 output d at a r a te (hz) 1k 10k noise free resolution (bits) gain = 1 gain = 8 gain = 16 gain = 32 gain = 64 gain = 128 figure 19 . noise free resolution (sinc 4 filter, chop disabled, v ref = 5 v) 08367-019 10 12 14 16 18 20 22 24 1 10 100 1k 10k output d at a r a te (hz) noise free resolution (bits) gain = 1 gain = 8 gain = 16 gain = 32 gain = 64 gain = 128 figure 20 . noise free resolution (sinc 3 filter, chop disabled, v ref = 5 v) 08367-022 16 17 18 19 20 22 21 23 1 10 100 1k output d at a r a te (hz) noise free resolution (bits) gain = 1 gain = 8 gain = 16 gain = 32 gain = 64 gain = 128 figure 21 . noise free resolution in fast settling mode (v ref = 5 v, averaging by 16, sinc 4 filter, chop disabled)
AD7193 data sheet rev. d | page 18 of 56 rm s noise and resoluti on the foll owing tables show the rms noise, peak - to - peak noise , effective resolution , and noise free (peak - to - peak) resolution of the AD7193 for various output data rates and gain settings with chop disabled for the sinc 4 and sinc 3 fi lters and for fast settling mode. the numbers given are for the bipolar input range with an external 5 v referen ce. these numbers are typical and are generated with a differential input voltage of 0 v when the adc is continuously converting on a single cha nnel. it is important to note that the effective resolution is calculated using the rms noise, wher eas the p eak - to - peak resolution is calculated based on peak - to - peak noise. the p eak - to - p eak resolution represents the resolution for which there is no code f licker. with chop enabled, the resolution improves by 0.5 bits . sinc 4 chop disabled table 7 . rms noise (nv) vs. gain and output data rate filter word (decimal) output data rate (hz) settling time (ms) gain of 1 8 16 32 64 128 1023 4.7 852.5 340 53 34 18 12 1 1 640 7.5 533 410 67 40 24 1 4 13 480 10 400 460 76 45 28 16 15 96 50 80 950 150 80 50 37 31 80 60 66.7 1000 160 90 54 40 35 32 150 26.7 1600 250 140 83 63 55 16 300 13.3 2300 340 190 120 90 79 5 960 4.17 4200 610 350 210 160 140 2 2400 1.67 7100 1000 570 350 260 230 1 4800 0.83 26, 000 3400 1700 910 530 380 table 8 . peak -to - peak noise (nv) vs. gain and output data rate filter word (decimal) output data rate (hz) settling time (ms) gain of 1 8 16 32 64 128 1023 4.7 852.5 2200 340 190 110 7 0 65 640 7.5 533 2 7 00 4 1 0 2 3 0 1 3 0 90 85 480 10 400 3000 450 260 1 5 0 100 95 96 50 80 6000 890 500 3 2 0 230 200 80 60 66.7 6600 1000 5 6 0 3 5 0 250 220 32 150 26.7 10, 000 1 5 00 920 5 4 0 400 3 7 0 16 300 13.3 14, 000 2200 1 3 00 800 6 0 0 5 3 0 5 960 4.17 28, 000 4 1 00 2400 1 4 00 100 0 9 00 2 2400 1.67 49, 000 7 0 00 3800 2 4 00 1 8 00 1 7 00 1 4800 0.83 1 75, 000 2 3 , 000 12, 000 6 1 00 3500 2 6 00 table 9 . effective resolution (peak -to - peak resolutio n) vs. gain and output data rate filter word (decimal) output data rate (hz) settling time (ms) gain of 1 1 8 16 32 64 128 1023 4.7 852.5 24 (22. 1 ) 24 (2 1 . 8 ) 24 (21.6) 24 (21.4) 23.6 (21. 1 ) 22. 8 (20.2) 640 7.5 533 24 (2 1.8 ) 24 (2 1.5 ) 23.9 (21.4) 23. 6 (21.2) 23. 4 (20. 7 ) 22.5 (19.8 ) 480 10 400 24 (21.7) 24 (21.4) 23.7 (21.2) 23.4 (21) 23.2 (20. 6 ) 22.3 (19. 6 ) 96 50 80 23.3 (20.7) 2 3 (20.4) 22.9 (20.3 ) 22.6 (19.9 ) 22 (19.4) 21. 3 (18.6 ) 80 60 66.7 23.3 (20.5) 22.9 (20.3) 22.8 (20.1 ) 22.5 (19.8) 21.9 (19.3) 21.1 (18.4) 32 150 26.7 22. 6 (19.9) 22. 3 (19. 7 ) 22. 1 (19.4 ) 21.8 ( 19.1 ) 21.2 (18.6) 20.4 (17.7 ) 16 300 13.3 22. 1 (19.4) 21.8 (19.1) 21.6 (18.9 ) 21.3 (18.6 ) 20.7 (18 ) 19.9 (17.2 ) 5 960 4.17 21. 2 (18.4 ) 2 1 (18.2 ) 20. 8 (18) 20.5 (17.8 ) 19. 9 (17.3) 19. 1 (16.4 ) 2 2400 1.67 20.4 (17.6 ) 20. 3 (17.4 ) 20. 1 (17.3 ) 19. 8 (17 ) 19. 2 (16.4 ) 18. 4 (15.5 ) 1 4800 0.83 18. 6 (15.8 ) 18. 5 (15. 7 ) 18. 5 (15.7) 18. 4 (15.6) 18. 2 (15.4 ) 17.6 (14.9 ) 1 t he output peak - to - peak (p - p) resolution is listed in parentheses.
data sheet AD7193 rev. d | page 19 of 56 sinc 3 chop disabled table 10 . rms noise (nv) vs . gain and output data rate filter word (decimal) output data rate (hz) settling time (ms) gain of 1 8 16 32 64 128 1023 4.7 639.4 340 58 35 20 13 11 640 7.5 400 4 1 0 72 41 25 16 14 480 10 300 4 9 0 90 4 5 28 18 16 96 50 60 100 0 160 85 54 38 34 8 0 60 50 1100 170 95 59 41 37 32 150 20 1700 260 150 88 66 59 16 300 10 2400 3 5 0 200 130 94 85 5 960 3.13 6400 870 470 270 190 160 2 2400 1.25 115 , 000 14, 000 7000 3 6 00 1800 9 5 0 1 4800 0.625 860, 000 110, 000 54, 000 27, 000 1 4 , 0 00 7000 table 11 . peak -to - peak noise (nv) vs. gain and output data rate filter word (decimal) output data rate (hz) settling time (ms) gain of 1 8 16 32 64 128 1023 4.7 639.4 2200 3 5 0 220 1 3 0 80 65 640 7.5 400 2 7 00 450 2 7 0 1 6 0 100 88 480 10 300 3000 520 310 1 8 0 1 2 0 100 96 50 60 6 400 9 90 540 370 250 230 80 60 50 7000 1100 6 1 0 390 270 250 32 150 20 11, 000 1 7 00 980 580 4 40 390 16 300 10 16, 000 2 3 00 1 4 00 860 6 30 560 5 960 3.13 40, 000 5700 3100 1 8 00 1 3 00 1100 2 2400 1.25 7 3 0 , 000 9 3 , 000 4 7 , 000 2 4 , 00 0 1 2 , 000 6 1 00 1 4800 0.625 5 , 7 00 , 000 73 0 , 000 36 0 , 000 18 0 , 000 93 , 000 45 , 000 table 12 . effective resolution (peak-to - peak resolution) vs. gain and output data rate filter word (decimal) output data rate (hz) settling time (ms) gain of 1 1 8 16 32 64 128 1023 4.7 639.4 24 (22. 1 ) 24 (2 1.8 ) 2 4 (21. 4 ) 23. 9 (21. 2 ) 23.5 (20.9 ) 22.8 (20.2) 640 7.5 400 24 (2 1.8 ) 24 (21.4) 23.9 (21.1 ) 23.6 (20.9 ) 23.2 (20.6 ) 22.4 (19.8) 480 10 300 24 (21.7) 23.8 (21. 2 ) 23. 7 (20.9 ) 23.4 (20.7 ) 23 (20. 3 ) 22.2 (19.6 ) 96 50 60 23.3 (20. 6 ) 22.9 (20.3 ) 22 .9 ( 20.1 ) 22.5 (19.7) 22 (19.3) 21.1 (18.4) 80 60 50 23.1 (20. 4 ) 22.8 (20.1) 22.7 (20 ) 22.3 (19.6) 21.9 (19.1) 21 (18.3) 32 150 20 22.5 (19.8) 22.2 (19. 5 ) 22 (19.3 ) 21.8 (19 ) 21.2 (18. 4 ) 20.3 (17.6) 16 300 10 22 (19.3) 21.8 (19.1) 21.6 (18.8 ) 21.2 (18.5 ) 20.7 (17.9 ) 19.8 (17.1 ) 5 960 3.13 20.6 (17.9) 20.5 (17. 7 ) 20.3 (17.6) 20.1 (17.4 ) 19.6 (16.9 ) 18.9 (16.1) 2 2400 1.25 16.5 (13.7) 16.4 (13.7) 16.4 (13. 7 ) 16.4 (13.7 ) 16.4 (13.7 ) 16.4 (13.6) 1 4800 0.625 13.5 (10. 8 ) 13.5 (10. 7 ) 13.5 (10.7 ) 13.5 (10.7 ) 13. 5 (10.7 ) 13.5 (10.7 ) 1 t he output peak - to - peak (p - p) resolution is listed in parentheses.
AD7193 data sheet rev. d | page 20 of 56 f ast s ettling table 13 . rms noise (nv) vs. gain and output data rate filter word (decimal) average output data rate (hz) settling time (ms) gain of 1 8 16 32 64 128 96 16 2.63 380 380 87 52 33 15 1 1 30 16 8.4 118.75 6 20 14 0 71 4 3 30 21 6 16 42.10 23.75 1300 2 7 0 1 5 0 82 5 6 4 7 5 16 50.53 19.79 1500 2 8 0 1 6 0 88 61 50 2 16 126.32 7.92 2300 3 8 0 210 1 3 0 88 77 1 16 252.63 3.96 3400 520 2 9 0 180 1 3 0 1 10 table 14 . peak -to - peak noise (nv) vs. gain and output data rate filter word (decimal) average output data rate (hz) settling time (ms) gain of 1 8 16 32 64 128 96 16 2.63 380 2500 450 260 180 1 0 0 70 30 16 8.4 118.75 4 0 0 0 9 00 470 280 1 90 1 3 0 6 16 42.10 23.75 8 5 00 1 8 00 95 0 5 4 0 3 60 30 0 5 16 50.53 19.79 9 5 00 1 9 00 1000 5 8 0 3 9 0 330 2 16 126.32 7.92 1 4 , 000 2 8 00 1 5 00 8 5 0 580 5 1 0 1 16 252.63 3.96 2 2 , 000 3800 2 0 00 1200 820 740 table 15 . effective resol ution (peak -to - peak resolution) vs. gain and output data rate filter word (decimal) average output data rate (hz) settling time (ms) gain of 1 1 8 16 32 64 128 96 16 2.63 380 24 (21.9) 2 3 .8 (2 1 . 4 ) 2 3 . 5 (2 1.2 ) 2 3 . 2 (20 .7 ) 2 3 . 2 (20 .6 ) 22. 8 (20.1 ) 30 16 8.4 118.75 2 3.9 (21. 3 ) 2 3 .6 (2 0 .4 ) 2 3 . 1 (20.3 ) 2 2 . 8 (20.1 ) 22. 3 (19.6 ) 21. 8 (19. 2 ) 6 16 42.10 23.75 22.9 (20.2) 22. 1 (19.4 ) 22 (19.3 ) 2 1 . 9 (19.1 ) 21. 4 (18. 7 ) 20.7 (18 ) 5 16 50.53 19.79 22.7 (20 ) 22. 1 (19.3 ) 2 1 . 9 (19.3 ) 2 1.8 (19 ) 21. 3 (18. 6 ) 20.6 (17.9 ) 2 16 126.32 7.92 22.1 (19. 4 ) 21. 6 (18.8 ) 21. 5 (18.7 ) 21. 2 (18.5 ) 20.8 (18 ) 20 (17 .2 ) 1 16 252.63 3.96 21.5 (18.8 ) 21. 2 (18.3 ) 21 (18.3 ) 20.7 (18) 20. 2 (17.5 ) 19.4 (16.7 ) 1 t he output peak - to - peak (p - p) resolu tion is listed in parentheses.
data sheet AD7193 rev. d | page 21 of 56 on- chip registers the adc is controlled and configured via a number of on - chip r egisters that are described on the following pages wherein the term set implies a logic 1 state and the term cleared implies a logic 0 state, unless otherwise noted. table 16. register summary register addr. dir. default bit 7 bi t 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 communications 00 w 00 wen r/ w register a ddress cread 0 0 status 00 r 80 rdy err noref parity chd3 chd2 chd 1 chd0 mode 01 r/w 080060 mode s elect dat _sta clk1 clk0 avg1 avg0 s inc 3 0 enpar clk_div s ingle rej60 fs9 fs8 fs7 fs6 fs5 fs4 fs3 fs2 fs1 fs0 (lsb) configuration 02 r/w 000117 c hop (msb) 0 0 refsel 0 p seudo s hort t emp ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 b urn refdet 0 buf u/ b g2 g1 g0 (lsb) data 03 r 00 0000 d 23 ( m sb) d 22 d 21 d 20 d 19 d 18 d 1 7 d 16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 (lsb) id 04 r x 2 x x x x 0 0 1 0 gpocon 05 r/w 00 0 bpdsw gp32en gp10en p3dat p2dat p1dat p0dat offset 06 r/w 800000 of23 (msb) of22 of21 of20 of19 of18 of17 of16 of15 of14 of13 of12 of11 of10 of9 of8 of7 of6 of5 of4 of3 of2 of1 of0 (lsb) full scale 07 r/w 5xxxx0 fs23 (msb) fs22 fs21 fs20 fs19 fs18 fs17 fs16 fs15 fs14 fs13 fs12 fs 11 fs10 fs9 fs8 fs7 fs6 fs5 fs4 fs3 fs2 fs1 fs0 (lsb)
AD7193 data sheet rev. d | page 22 of 56 communications regis ter rs2, rs1, rs0 = 00 0 the communications register is an 8 - bit write - only register. all communications to the part must start with a write operation to the communications r egister. the data written to the com muni - cations register determine whether the next operation is a read or writ e operation and in which register this operation occurs . for read or write operatio ns, when the subsequent read or write oper - ation to the selec ted re gister is complete, the interface return s to w here it expects a write operation to the communi cations register. this is the default state of the inter face and, on power - up or after a reset, the adc is in this default state w aiting for a write operati on to the communications register. in situations where the interface sequence is lost, a write operation of at least 40 serial clock cycles with din high returns the adc to this default state by resetting the entire part. table 17 outlines the bit designations for the communications register. cr0 through cr7 indicate the bit location, cr deno ting that the bits are in the communications register. cr7 denotes the first bit of the d ata stream. the number in parentheses indicates th e power - on/reset default status of that bit. cr7 cr6 cr5 cr4 cr3 cr2 cr1 cr0 wen (0) r/ w (0) rs2(0) rs1(0) rs0(0) c read (0) 0(0) 0(0) table 17 . communications register (cr) bit designations bit location bit name description cr7 wen write e nable b it. for a write to the communications register to occur, 0 must be written to this bit. if a 1 is the first bit written, the part does not clock on to subsequen t bits in the register ; rather, i t stay s at this bit location until a 0 is written to this bit. after a 0 is written to the wen bit, the next seven bits are loaded to the communications register. i dling the din pin high betw een data transfers minimizes the effects of spurious sclk pulses on the serial interface . cr6 r/ w 0 in this bit location indicates that the next operation is a write to a specified register. 1 in this bit position indicates th at the next operation is a read from the designated register. cr5 to cr3 rs2 to rs0 register a ddress bit s. these address bits are used to select which registers of the adc are selected during the serial interface communication (s ee table 18) . cr2 c read continuous read of the d ata r egister. when this bit is set to 1 (and the data register is selected), the serial interface is configured so that the data re gister can be continuously read; that is, the contents of the data r egister are automatically placed on the dout pin when the sclk pulses are applied after the rdy pin goes low to indicate that a conversion is complete. the communications register does not have to be written to for subsequent data re a ds. to enable continuous read , i nstruction 01011100 must be written to the communications register. to disable continuous read, i nstruction 01011000 must be written to the communica - tions register while the rdy pin is low. while con tinuous read is enabled, the adc monitors activity on the din line so that it can receive the instruction to disable continuous read. additi onally, a reset occur s if 40 consecutive 1s occur on din ; t herefore, hold din low until an instruction is written to the device. cr1 to cr0 0 these bits must be programmed to logic 0 for correct operation. table 18 . register selection rs2 rs1 rs0 register register size 0 0 0 communications r egiste r during a write o peration 8 bit s 0 0 0 status register during a read o peration 8 bit s 0 0 1 mode r egister 24 bit s 0 1 0 configuration r egister 24 bit s 0 1 1 data register/d ata r egister plus status i nformation 24 bit s / 32 bit s 1 0 0 i d r egister 8 bit s 1 0 1 g pocon r egister 8 bit s 1 1 0 offset r egister 24 bit s 1 1 1 full - scale r egister 24 bit s
data sheet AD7193 rev. d | page 23 of 56 s tatus register rs2, rs1, rs 0 = 00 0; power - on/reset = 0x80 the status register is an 8 - bit read - only register. to access the adc status register, the user must write to the communications register, select the next operation to be a read operation , and load bit rs2, bit rs1, and bit rs0 with 0. table 19 outlines the bit designations for the s tatus register. sr0 through sr7 indicate the bit locations , sr denoting that the bits are in the status register. sr7 denotes the first bit of the data stream. the number in paren - theses indicates the power - on/reset default status of that bit. sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 rdy (1) err(0) noref(0) p arity (0) chd3(0) chd2(0) chd1(0) chd0(0) table 19 . status register (sr) bit designations bit location bit name description sr7 rdy ready b it for the a dc. this bit is c leared when data is written to the adc data register. the rdy bit is set automatically after the adc data register is read , or a period of time before the data register is updated , with a new conversion result to ind icate to the user that the conversion data should not be read . it is also set when the p art is placed in power - down mode or idle mode or when sync is taken low. the end of a conversion is also indicated by the dout/ rdy pin. this pin can be used as an alternative to the status register for monitoring the adc for conversion data. sr6 err adc err or bit . this bit is written to at the same time as the rdy bit. this bit is s et to indicate th at the result written to the adc data register is clamped to all 0s or all 1s. error sources include overrang e, underrange , or the absence of a reference voltage. this bit is c leared when the result written to the data register returns to within the allowe d analog input range . the err bit is also set during calibrations if the reference source is invalid or if the applied analog input voltages are outside range during system calibrations. sr5 noref no external reference b it. this bit is s et to indicate t hat the selected reference (refin1 or refin2) is at a voltage that is below a specified threshold. when set, conversion results are clamped to all 1s . this bit is c leared to indicate that a valid reference is applied to the selected reference pins. the nor ef bit is e nabled by setting the ref det bit in the configuration register to 1. sr4 p arity parity c heck of the d ata r egister. if the enpar bit in the mode register is set and there is an odd number of 1s in the data register , the parity bit is set . it i s cleared if there is an even number of 1s in the data register. the dat_sta bit in the mode register should be set when the parity check is used. when the dat_sta bit is set, the contents of the status register are transmitted along with the data for each data register read. sr 3 to sr0 chd 3 to chd0 these bits indicate which channel corresponds to the data register contents. they do not indicate which channel is presently being converted but indicate which channel was selected when the conversion contai ne d in the data register was generated.
AD7193 data sheet rev. d | page 24 of 56 mode register rs2, rs1, rs0 = 0 01; power - on/reset = 0x080060 the mode register is a 24 - bit register from which data can be read or to which data can be written. this register is used to select the operating mode, the output data rate, and the clock source. table 20 outlines the bit designations for the mode register. mr0 through mr23 indicate the bit locations, mr denoting that the bits are in the mode register. mr23 denotes the first bit of the data stream. the number in parentheses indicates the power - on/reset default status of that bit. any write to the mode register resets the modulator and filter and sets the rdy bit. mr23 mr22 mr21 mr20 mr19 mr18 mr17 mr16 md2(0) md1(0) md0(0) dat_sta(0) clk1(1) clk0(0) avg1(0) avg0(0) mr15 mr14 mr13 mr12 mr11 mr10 mr9 mr8 sinc 3(0) 0 enpar(0) clk_div ( 0 ) s ingle (0) rej60(0) fs9(0) fs8(0) mr7 mr6 mr5 mr4 mr3 mr2 mr1 mr0 fs7(0) fs6(1) fs5(1) fs4(0) fs3(0) fs2(0 ) fs1(0) fs0(0) table 20 . mode register (mr) bit designations bit location bit name description mr23 to mr21 md2 to md0 mode s elect b its. these bits select the operati ng mode of the AD7193 (see table 21). mr20 dat_sta this bit enables the t ransmi s s ion of status register contents after each data register read. when dat_sta is set, the contents of the status register are transmitted along with each data register read. this function is useful whe n several channels are selected because the status register identifies the channel to which the data register value corresponds. mr19 , mr18 clk1, clk0 these bits select the clock source for the AD7193 . either the on - chip 4.92 mhz clock or an external cl ock can be used. the ability to use an external clock allows several AD7193 devices to be synchronized. also, 50 hz/60 hz rejection is improved when an accurate external clock drives the AD7193 . clk1 clk0 adc clock source 0 0 external crystal. the external crystal is connected from mclk1 to mclk2. 0 1 external clock . the external clock is applied to the mclk2 pin. 1 0 internal 4.92 mhz clock. pin mclk2 is tri stated. 1 1 internal 4.92 mhz clock. the internal clock is available on m clk2. mr17, mr16 avg1, a vg 0 fast settling fil ter. when this option is selected, the settling time equals one conversion time. in fast settling mode, a first - o rder average and decimate block is included after the sinc filter . the data from the sinc filter is averaged by 2, 8 , or 16. the averaging reduces the output data rate for a given fs word ; h owever, the rms noise improve s . the avg1 and avg0 bits select the amount of averaging. fast settling mode can be used for fs words less than 512 only . when the si nc 3 filter is selected, the fs word must be less than 256 when averaging by 16. avg1 avg0 average 0 0 no averaging ( fast settling mode disabled) 0 1 average by 2 1 0 average by 8 1 1 average by 16 mr15 s inc 3 sinc 3 f ilter s elect b it . when t his bit is cleared, the sinc 4 filter is used (default value). when this bit is set, the s inc 3 filter is used. the benefit of the sinc 3 filter compared to the sinc 4 filter is its lower settling time. for a given output data rate , f adc , the sinc 3 filter has a settling time of 3/ f adc w h er e a s the sinc 4 filter has a settling time of 4/ f adc when chop is disabled . the sinc 4 filter, due to its deeper notches, gives better 50 hz/60 hz rejection. at low output data rates, both filters give similar rms noise and simi lar no missing codes for a given output data rate. at higher output data rates (fs values less than 5), the sinc 4 filter gives better performance than the sinc 3 filter for rms noise and no missing codes. mr14 0 this bit must be programmed with a logic 0 f or correct operation. mr13 enpar enable p arity b it. when enpar is set , parity checking on the data register is enabled. the dat_sta bit in the mode register should be set when the parity check is used. when the dat_sta bit is set, the contents of the stat us register are transmitted along with the data for each data register read.
data sheet AD7193 rev. d | page 25 of 56 bit location bit name description mr12 clk_div clock d ivide -by - 2. when clk_div is set, the master clock is divided by 2. for normal conversions, set this bit to 0. when performing internal full - scale calibrations , this bit must be se t when av dd is less than 4.75 v. the calibration accuracy is optimized when chop is enabled and a low output data rate is used while performing the calibration. when av dd is greater than or equal to 4.75 v, it is not compulsory to set the clk_div bit when performing internal full - scale calibrations . mr11 s ingle single c ycle c onversion e nable b it. when this bit is set, the AD7193 settles in one conversion cycle so that it functions as a zero latency adc. this bit has no effect when mult iple analog input channels are enabled or when the single conversion mode is selected. if the average + decimate filter is enabled, this b it ( single ) does not have an effect on the conversions unless chopping is also enabled. mr10 rej60 this bit e nables a notch at 60 hz when the first notch of the sinc filter is at 50 hz. when rej60 is set, a filter notch is placed at 60 hz when the sinc filter first notch is at 50 hz. this allows simultaneous 50 hz/ 60 hz rejection. mr9 to mr0 fs9 to fs0 filter o utput d ata r ate select b its. the 10 bits of data programmed into these bits determine the filter cutoff frequency, the position of the first notch of the filter , and the output data rate for the part . in association with the gain selection , they also determine t he output no ise and, therefore, the effective resolution of the device (see table 7 through table 15). when chop is disabled , fast settling mode is disabled and continuous conversion mode is selected . out put data rate = ( mclk /1024 )/ fs where fs is the decimal equivalent of the code in b it fs0 to bit fs9 with in the range of 1 to 1023 , and mclk is the master clock frequency. with a nominal mclk of 4.92 mhz, this results in an output data rate from 4.69 hz to 4.8 khz. with chop disabled and fast settling mode disabled , the first notch frequency is equal to the output data rate when converting on a single channel. when chop is enabled (fast settling mode disabled) output data rate = ( mclk /102 4)/( n fs ) where fs is the dec imal equivalent of the code in b it fs0 to bit fs9 with in the range of 1 to 1023 , and mclk is the master clock frequency. with a nominal mclk of 4.92 mhz, this results in a conversion rate from 4.69/n hz to 4.8/n khz , where n is the order of t he sinc filter. the first notch frequency of the sinc filter is equal to n output data rate the chopping introduces notches at odd integer multiples of output data ra te/2 table 21 . operating modes (md) md2 md1 md0 mode 0 0 0 continuous c onversion m ode ( d efault). in continuous conversion mode, the adc continuously performs conversions and places the result in the data register. the dout/ rdy pin and the rdy bit in the status re gister go low when a conversion is complete. the user can read these conversions by setting the c read bit in the commun - ications register to 1, which enables continuous read. when continuous read is enabled, the conversions are automatically placed on the dout line when sclk pulses are applied. alternatively, the user can instruct the adc to output each conversion by writing to the communications register. after power - on, a reset , or a re configuration of the adc, the complete settling time of the filter is required to generate the first valid conversion. subsequent conversions are available at the selected output data rate , which is dependent on filter choice. 0 0 1 single c onversion m ode. when single conversion mode is selected, the adc powers up and pe rforms a single conversion on the selected channel. the internal clock requires up to 1 ms to power up and settle. the adc then performs the conversion , which requires the complete settling time of the filter. the conversion result is placed in the data re gister. rdy goes low, and the adc returns to power - down mode. the conversion remains in the data register until another conversion is performed. rdy remains active (low) until the data is read or another conver sion is performed. 0 1 0 idle m ode. in idle mode, the adc filter and modulator are held in a reset state even though the modulator clocks continue to be provided. 0 1 1 power - d own m ode. in power - down mode, all AD7193 circuitry, except the bridge po wer - down switch, is powered down. the bridge power - down switch remains active because the user may need to power up the sensor prior to powering up the AD7193 for settling reasons. the external crystal, if selected, remains active.
AD7193 data sheet rev. d | page 26 of 56 md2 md1 md0 mode 1 0 0 internal zero - scale c alibration. an internal short is automatically connected to the input. rdy goes high when the calibration is initiated and returns low when the calibration is complete. the adc is placed in idle mode following a calibration. t he measured offset coefficient is placed in the offset register of the selected channel. 1 0 1 internal f ull -s cale c alibration. a full - scale input voltage is automatically connected to the input for this calibration. rdy goes hig h when the calibration is initiated and returns low when the calibration is complete. the adc is placed in idle mode following a calibration. the measured full - scale coefficient is placed in the full - scale register of the selected channel. a full - scale cal ibration is re commended each time that the gain of a channel is changed to minimize the full - scale error. when av dd is less than 4.75 v, the clk_div bit must be set when performing the internal full - scale calibration. 1 1 0 system z ero -s cale c alibratio n. the u ser should connect the system zero - scale input to the channel input pins as selected by the ch7 to ch0 bits in the configuration register . rdy goes high when the calibration is initiated and returns low when the calibration i s complete. the adc is placed in idle mode following a calibration. the measured offset coe fficient is placed in the offset register of the selected channel. a system zero - scale calibration is re commend ed each time th at the gain of a channel is changed. 1 1 1 system f ull -s cale c alibration. the u ser should connect the system full - scale input to the channel input pins as selected by the ch7 to ch0 bits in the configuration register . rdy goes high when the calibration is initiated an d returns low when the calibration is complete. the adc is placed in idle mode following a calibration. the measured full - scale coefficient is placed in the full - scale reg ister of the selected channel. a full - scale calibration is recommende d each time the gain of a channel is changed.
data sheet AD7193 rev. d | page 27 of 56 configuration regist er rs2, rs1, rs0 = 010; power - on/reset = 0x000117 the configuration register is a 24 - bit register from which data can be read or to which data can be written. this register is used to configure the adc for unipolar or bipolar mode, to enable or disable the buffer, to enable or disable the burnout currents, to select the gain, and to select the analog input channel. table 22 ou tlines the bit designations for the configuratio n register. con0 through con23 indicate the bit locations. con denotes that the bits are in the configuration register. con23 denotes the first bit of the data stream. the number in parenthese s indicates the power - on/reset default status of that bit. co n23 con22 con21 con20 con19 con18 con17 con16 c hop (0) 0(0) 0(0) refsel(0) 0(0) p seudo (0) s hort (0) temp (0) con15 con14 con13 con12 con11 con10 con9 con8 ch7(0) ch6(0) ch5(0) ch4(0) ch3(0) ch2(0) ch1(0) ch0(1) con7 con6 con5 con4 con3 con2 con1 con0 b urn (0) refdet(0) 0(0) buf(1) u/ b (0) g 2(1) g 1(1) g 0(1) table 22 . configuration register (con) bit designations bit location bit name description con23 c hop chop e nable b it. when the chop bit is cleared, chop is disabled. with chop disabled, higher conversion rates are allowed. for an fs word of 96 decimal and the sinc 4 filter selected, the conversion time is 20 ms and the settling time is 80 ms. however, at low gains, periodic calibrations may be required to remove the offset and offset drift. when the chop bit is set, chop is enabled. when chop is enabled, the offset and offset drift of the adc are continuously removed. however, this increases the conversion time and settling time of th e adc. for example, when fs = 96 decimal and the sinc 4 filter is selected, the conversion time with chop enabled equals 80 ms and the settling time equals 160 ms. con22, con21 0 these bits must be programmed with a logic 0 for correct operation. con20 refsel reference s elect b its. the reference source for the adc is selected using these bits. refsel reference voltage 0 external reference applied between refin1(+) and refin1(?). 1 external reference applied between the p1/refin2(+) and p0/refin2(?) pins. con19 0 this bit must be programmed with a logic 0 for correct operation. con18 p seudo pseudo differential analog inputs. the analog inputs can be configured as differential inputs or pseudo differential analog inputs. when the pseudo bit is set to 1, the AD7193 is configured to have eight pseudo differential analog inputs. when pseudo bit is set to 0, the AD7193 is configure d to have four differential analog inputs. con1 7 to con8 s hort , temp , ch7 to ch0 channel s elect b its. these bits select which channels are enabled on the AD7193 (s ee table 23 and table 24) . several chann els can be selected , and the AD7193 automatically sequence s them. the conversion on each channel require s the complete settling time. when performing calibrations or when accessing the calibration registers, only one channel can be selected. con7 b urn whe n this bi t is set to 1 , the 500 na current sources in the signal path are enabled. when burn = 0, the burnout currents are disabled. the burnout currents can be enabled only when the buffer is active and when chop is disabled. con6 refdet enables the re ference detect function. when set, the noref bit in the status register indicates when the external reference being used by the adc is open circuit or less than 0. 6 v maximum. the reference detect circuitry operates only when the adc is active. con5 0 thi s bit must be programmed with a logic 0 for correct operation.
AD7193 data sheet rev. d | page 28 of 56 bit location bit name description con4 buf enables the buffer on the analog i nputs. if buf is set, the analog inputs are buffered, allowing the user to place source impedances on the front end without contributing gain e rrors to the system. when the buffer is enabled, it requires some head - room; therefore, the voltage on any input pin must be limited to 250 mv within the power supply rails . i f cleared, the analog inputs are unbuffered, lowering the power consumption of the device. with the buffer disabled, the voltage on the analog input pins can be from 50 mv below agnd to 50 mv above av dd . con3 u/ b polarity s elect b it. when this bit is set, unipolar operation is selected. when this bit is cleared, bipolar operation is selected. con2 to con0 g2 to g0 gain s elect b its. these bits are w ritten by the user to select the adc input range as follows: g2 g1 g0 gain adc input range ( 2. 5 v reference) 0 0 0 1 2. 5 v 0 0 1 reserved 0 1 0 reserved 0 1 1 8 312.5 mv 1 0 0 16 156.2 mv 1 0 1 32 78.125 mv 1 1 0 64 39.06 mv 1 1 1 128 19.53 mv table 23 . channel selection (p seudo bit = 0) channel enable bits in the configuration register channel ena bled status register bits chd[3:0] calibration register pair short temp ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 positive input ain(+) negative input ain(?) 1 ain1 ain2 0 000 0 1 ain3 ain4 0 001 1 1 ain5 ain6 0010 2 1 ain7 ain 8 0 011 3 1 ain1 ain 2 0 100 0 1 ain3 ain 4 0 101 1 1 ain5 ain 6 0 110 2 1 ain7 ain 8 0 111 3 1 temperature s ensor 1000 1 ain2 ain2 1001 0 table 24 . channel selection (p seudo bit = 1 ) channel enable bits in the configuration register channel enabled status register bits chd[3:0] calibration register pair s hort temp ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 positive input ain(+) negative input a in(?) 1 ain1 ain com 0 000 0 1 ain2 aincom 0 001 1 1 ain3 aincom 0010 2 1 ain4 aincom 0 011 3 1 ain5 aincom 0 100 4 1 ain6 aincom 0 101 4 1 ain7 aincom 0 110 4 1 ain8 aincom 0 111 4 1 temperature s ensor 1000 1 ain com ain com 1001 0
data sheet AD7193 rev. d | page 29 of 56 data register rs2, rs1, rs0 = 011; power - on/reset = 0x000000 the conversion result from the adc is stored in this data register. this is a read - only , 24 - bit register. upo n completi on of a read operation from this register, the rdy pin/bit is set. when the dat_sta bit in the mode register is set to 1, the contents of the status register are appended to each 24 - bit conversion. this is advis able when several anal og input channels are enabled because the four lsbs of the status register (chd 3 to chd0) identify the channel from which the conversion originated. id register rs2, rs1, rs0 = 100; power - on/reset = 0xx 2 the identific ation number for the AD7193 is stored i n the id register. this is a read - only register . gpocon register rs2, rs1, rs0 = 10 1; power - on/reset = 0x00 the gpocon register is an 8 - bit register from which data can be read or to which data can be written. this register is used to enable the general - pu rpose digital outputs. table 25 outlines the bit designations for the gpocon register. gp0 through gp7 indicate the bit locations. gp denotes that the bits are in the gpocon register. gp7 denotes the first bit of the data stre am. the number in parentheses indicates the power - on/reset default status of that bit. gp7 gp6 gp5 gp4 gp3 gp2 gp1 gp0 0(0) bpdsw(0) gp32en(0) gp10en(0) p3dat(0) p2dat(0) p1dat(0) p0dat(0) table 25. gpocon register (gp) bit designations bit location bit name description gp7 0 this bit must be programmed with a logic 0 for proper operation. gp6 bpdsw bridge p ower - down s witch c ontrol b it. this bit is set by the user to close the bridge power - down switch b pdsw to agnd. the switch can sink up to 30 ma. the bit is cleared by the user to open the bridge power - down switch. when the adc is placed in power - down mode, the bridge power - down switch remains active. gp5 gp32en digital output p3 and digital outp ut p2 e nable. when gp32en is set, the p3 and p2 digital outputs are active. when gp32en is cleared, the p3 and p2 pins are tristated, and the p3dat and p2dat bits are ignored. gp4 gp10en digital output p1 and digital output p0 e nable. when g p10en is set, the p1 and p0 digital outputs are active. the p1 and p0 pins can be used as a reference input to refin2 when the refsel bit in the configuration register is set to 1. when gp10en is cleared, the p1 and p0 outputs are tristated, and the p1d at and p0dat bits are ignored. gp3 p3dat digital output p3. when gp32en is set, the p3dat bit sets the value of the p3 general - purpose output pin. when p3dat is high, the p3 output pin is high. when p3dat is low, the p3 output pin is low. when th e gpocon register is read, the p3dat bit reflects the status of the p3 pin if gp32en is set. gp2 p2dat digital output p2. when gp32en is set, the p2dat bit sets the value of the p2 general - purpose output pin. when p2dat is high, the p2 output pin is h igh. when p2dat is low, the p2 output pin is low. when the gpocon register is read, the p2dat bit reflects the status of the p2 pin if gp32en is set. gp1 p1dat digital output p1. when gp10en is set, the p1dat bit sets the value of the p1 general - p urpose output pin. when p1dat is high, the p1 output pin is high. when p1dat is low, the p1 output pin is low. when the gpocon register is read, the p1dat bit reflects the status of the p1 pin if gp10en is set. gp0 p0dat digital output p0. when gp 10en is set, the p0dat bit sets the value of the p0 general - purpose output pin. when p0dat is high, the p0 output pin is high. when p0dat is low, the p0 output pin is low. when the gpocon register is read, the p0dat bit reflects the status of the p0 pi n if gp10en is set.
AD7193 data sheet rev. d | page 30 of 56 offset register rs2, rs1, rs0 = 11 0; power - on/reset = 0x800000) the offset register holds the offset calibration coefficient for the adc. the power - on reset value of the offset register is 0x800000 . the AD7193 has five offset regist ers . in differential mode, e ach channel has a dedicated offset register . in pseudo differential mode, channel ain1, channel ain2 , channel ain3 , and channel ain4 have dedicated registers wh ereas the remaining channels share an offset re gister (see table 23 and table 24). each of these registers is a 24 - bit read/write register. this register is used in conjunction with its associated full - scale register to form a register pair. the power - on reset value is au tomatically overwritten if an internal or system zero - scale calibration is initiated by the user. the AD7193 must be placed in power - down mode or idle mode when writing to the offset register. full - scale register rs2, rs1, rs0 = 111; power - on/reset = 0x 5xxxx0 the full - scale register is a 24 - bit register that holds the full - scale calibration coefficient for the adc. the AD7193 has five full - scale registe rs . in differential mode, each channel has a dedicated full - scale register. in pseudo differential mode , the ain1, ain2 , ain3 , and ain 4 channels have dedicated registers wh er e as the remaining c hannels share a full - scale register (see table 23 and table 24). the full - scale registers are read/write registers . however, when writing to the full - scale registers, the adc must be placed in power - down mode or idle mode. these registers are configured at power - on with factory calibrated full - scale calibration coeffi - cients, the calibration being performed at gain = 1. t herefore, every device has different default coefficients . the default value is automatically overwritten if an internal or system full - scale calibration is initiated by the user or if the full - scale register is written to.
data sheet AD7193 rev. d | page 31 of 56 adc circuit informat ion mclk1 mclk2 p0/refin2(?) p1/refin2(+) dv dd dgnd 5v ain1 in+ in? out? out+ ain2 ain3 ain4 aincom refin1(?) bpdsw agnd AD7193 refin1(+) reference detect serial interface and control logic temp sensor calibration clock circuitry av dd agnd dout/rdy din sclk cs sync p3 p2 av dd agnd ain5 ain6 ain7 ain8 modulator and filter - adc pga mux 08367-023 figure 22 . basic connection diagram overview the AD7193 is a n ultra low noise adc that incorporates a - modulator, a buffer , pga , and on - chip digital filtering intended for the measurement of wide dynamic range signals such as those in pressure transducers, weigh scales, and strain ga ge applications. figure 22 shows the basic connections required to operate the part. analog inputs the device can be configured to have four differential or eight pseudo differential analog inputs. the analog inputs can be buffered or unbuffered. multiplexer the on - chip multiplexer increases the channel count of the device. b e cause the multiplexer is included on chip, any channel changes are synchronized with the conversion process. pga the analog input signal can be amplified using the pga. t he pga allows gains of 1, 8, 16, 32, 64 , and 128. refe rence detect the AD7193 is capab le of monitor ing the external reference. if the reference is not present, a flag is set in the status register of the device . burnout currents two 500 na burnout currents are included on - chip to detect the presence of the ex ternal sensor. sigma - delta ( - ) adc and filter the AD7193 contain s a fourth - order - modulator followed by a digital filter. the device has several filter options ? sinc 4 ? sinc 3 ? chop enabled/di sabled ? fast s ettling ? zero l atency serial interface the AD7193 has a 4 - wire spi interface. th e on - chip registers are accessed via the serial interface. clock the AD7193 has an internal 4.92 mhz clock. either this clock or an ext ernal clock can be used as the clock source to the AD7193 . the internal clock can a lso be made available on a pin if a cl ock source is required for external circuitry . bridge power - down switch exter nal circuitry such as strain ga ges or bridges can be powered up/down using the bridge power - down switch. temperature sensor the on - chip temperature sensor monitors the die tempera ture. digital outputs the AD7193 has four general - purpose digital outputs. these can be used for driving external circuitry. for example, an external multiplexer can be controlled by these outputs. calibration both internal and system calibration are incl ude d on chip ; t herefore, the user has the option of removing offset/gain errors internal to the AD7193 only, or removing the offset/gain errors of the compl ete end system .
AD7193 data sheet rev. d | page 32 of 56 analog input channel the AD7193 has four differential/eight pseudo differential ana lo g input channels that can be buffered or unbuffered. in buffered mode (the buf bit in the configuration register is set to 1), the input channel feeds into a high impedance input stage of the buffer amplifier. therefore, the input can tolerate significan t source impedances and is tailored for direct connection to external resistive type sensors such as strain gages or resistance temperature detectors (rtds). when buf = 0, the part operate s in unbuffered mode. this results in a higher analog input current . note that this unbuffered input path provides a dynamic load to the driving source. therefore, resistor/capacitor combinations on the input pins can cause gain errors, depending on the output impedance of the source that is driving the adc input. table 26 shows the allowable external resistance/capacitance values for unbuffered mode at a gain of 1 such that no gain error at the 20 - bit level is introduced. table 26 . external rc combination for no 20 - bit gain error c (pf) r (?) 50 1.4 k 100 850 500 300 1000 230 5000 30 the absolute input voltage range in buffered mode is restricted to a range between agnd + 250 mv and av dd ? 250 mv. care must be taken in setting up the common - mode voltage to not exceed these limits ; o therwise, linearity and noise performance degrade . the absolute input voltage in unbuffered mode includes the range between agnd ? 50 mv and av dd + 50 mv. the negative absolute input volt age limit allow s the possibility of monito ring small true bipolar signals with respect to agnd. programmable gain ar ray (pga) when the gain stage is enabled, the output from the buffer is applied to the input of the pga. the presence of the pga means that signals of small amplitude can be gained within the AD7193 and still maintain excellent noise performance. for example, when the gain is set to 128, the rms noise is 11 nv, typically, when the output data rate is 4.7 hz, which is equivalent to 22. 7 bits of effective resolution or 20 bits of noise free resolution. the AD7193 can be programmed to have a gain of 1, 8, 16, 32, 64, or 128 by using bit g2 to bit g0 in the configuration register. therefore, with an external 2.5 v reference, the unipolar r anges are from 0 mv to 19.53 mv to 0 v to 2.5 v , and the bipolar ranges are from 19.53 mv to 2.5 v. t he analog input range must be limited to (av dd ? 1.25 v )/gain because the pga requires some headroom. therefore, if v ref = av dd = 5 v, t h e m aximum analog input that can be applied to the AD7193 is 0 v to 3.75 v/gain in unipolar mode or 3.75 v/gain in bipolar mode. reference the adc has a fully differe ntial input capability for the refer - ence channel. in addition, the user has the option of selecting one of two external reference options (refin1( ) or refin2( )). the reference source for the AD7193 is selected using the refsel bit in the configuration r egister. the refin2( ) pins are dual purpose: they can function as two general - purpose output pins or as reference pins. when the refsel bit is set to 1, these pins automatically function as reference pins. the common - mode range for these differential inpu ts is from agnd to av dd . the reference voltage refin (refinx(+) ? refinx(?)) is av dd nominal, but the AD7193 is functional with reference voltages from 1 v to av dd . in applications where the excitation (voltage or current) for the transducer on the analog input also drives the reference voltage for the part, the effect of the low frequency noise in the excitation source is removed because the application is ratiometric. if the AD7193 is u sed in a nonratiometric applica tion, a l ow noise reference should be u sed. the reference input is unb uffered; therefore, excessive r c source impedances introduce gain errors. rc values similar to those in table 26 are recommended for the reference inputs. d e riving the reference input voltage from an external resistor means that the reference input sees significant external source impedance. external decoupling on the refinx pins is not recommended in this type of circuit configuration. conversely, if large decoupling capacitors are used on the refere nce inputs, there should be no resistors in series with the reference inputs. recommended 2.5 v reference voltage sources for the AD7193 include the adr421 and adr43 1 , which are low noise references . these references tolerate decoupling capacitors on refinx(+) without introducing gain errors in the system. figure 23 shows the recommended connections between the adr421 and the AD7193. 4 2 0.1f a vdd adr421 AD7193 v in gnd refinx(+) refinx(?) v out trim 10f 4.7f 6 5 08367-124 figure 23 . adr421 to AD7193 connections
data sheet AD7193 rev. d | page 33 of 56 reference detect the AD7193 includes on - chip circuitry to detect whether the part has a valid reference for conversions or calibrations. this feature is enabled when the refdet bit in the configuration register is s et to 1. if the voltage between the selected refinx(+) and refinx(?) pins is less than 0 .3 v , the AD7193 detects that it no longer has a valid reference. in this case, the noref bit of the status register is set to 1. when the voltage between the selected refinx(+) and refinx(?) pins is greater than 0.6 v, the AD7193 detects a valid reference so the noref bit is set to 0. the operation of the noref bit is undefined when the voltage between the selected refinx(+) and refinx(?) pins is between 0.3 v and 0.6 v. if the AD7193 is performing normal conversions and the noref bit becomes active, the conversion result is all 1s. therefore, it is not necessary to continuously monitor the status of th e noref bit when performing conversions. it is only necessary to verify its status if the conversion result read from the adc data register is all 1s. if the AD7193 is performing either an offset or full - scale calibration and the noref bit becomes active , the updating of the respective calibration registers is inhibited to avoid loading incorrect coefficients to these registers, and the err bit in the status register is set. if the user is concerned about verifying that a valid reference is in place every time a calib ration is performed , the status of the err bit should be checked at the end of the calibration cycle. bipolar/unipolar con figuration the analog input to the AD7193 can accept either unipolar or bipolar input voltage ranges. a bipolar input r ange does not imply that the part can tolerate negative voltages with respect to system agnd. in pseudo differential mode, signals are referenced to aincom, w hereas in differential mode, signals are referenced to the negative input of the differential pai r. for example, if aincom is 2.5 v and the AD7193 ain1 analog input is configured for unipolar mode with a gain of 2, the input voltage range on the ain1 pin is 2.5 v to 3.75 v when a 2.5 v reference is used. if aincom is 2.5 v and the AD7193 ain1 analog input is configured for bipolar mode with a gain of 2, the analog input range on ain1 is 1.25 v to 3.75 v . the bipolar/unipolar option is chosen by programming the u/ b bit in the configuration register. data output coding when the a dc is configured for unipolar operation, the output code is natural (straight) binary with a zero differential input voltage resulting in a code of 0 00 0 00, a midscale voltage result ing in a code of 100 000, and a full - scale input voltage resulting in a co de of 111 111. the output code for any analog input voltage can be represented as code = (2 n ain gain )/ v ref when the adc is configured for bipolar operation, the output code is offset binary with a negative full - scale voltage resulting in a code of 00 0 000, a zero differential input voltage resulting in a code of 100 000, and a positive full - scale input voltage resulting in a code of 111 111. the output code for any analog input voltage can be represented as code = 2 n C 1 [( ain gain / v ref ) + 1] whe re : ain is the analog input voltage . gain is the pga setting (1 to 128) . n = 24. burnout currents the AD7193 contains two 500 na constant current generators, one sourcing current from av dd to ain(+) and one sinki ng current from ain(?) to agnd. the currents are switched to the selected analog input pair. both currents are either on or off, depending on the burnout current enable ( burn ) bit in the configuration register. these currents can be used to verify that an external transducer remains operational before attempting to take measurements on that channel. after the burnout currents are turned on, they flow in the external transducer circuit, and a measurement of the input voltage on the analog input channel can be taken. it takes some time for the burnout currents to detect an open circuit condition because the currents must charge any external capacitors. there are several reasons that a fault condition is detected : t he front - end sensor may be either open circui t or overloaded , or the reference may be absent and the noref bit in the status register is set, thus clamping the data to all 1s. the user must check these three cases before making a deter mination . if the voltag e measured is 0 v, it may indicate that th e transducer has short circuited. the current sources work over the normal absolute input voltage range specifications when the analog inputs are buffered and chop is disabled. channel sequencer the AD7193 includes a channel sequencer, which simplifies com munications with the device in multichannel applications. the sequencer also optimizes the channel throughput of the device because the sequencer switches channels at the optimum rate rather than waiting for instructions via the spi interface. bit ch0 to bit ch7 in the configuration register are used to enable the required analog input channels. the analog inputs must be configured for differential mode or pseudo differential mode using the pseudo bit in the configuration register. the tempera - ture sensor is enabled using the temp bit in the configuration. an internal short can also be selected using the short bit in the configuration register.
AD7193 data sheet rev. d | page 34 of 56 in continuous conversion mode, the adc selects each of the enabled channels in sequence and performs a conversi on on the channel. th e dout/ rdy pin indicates when a valid conversion is available on each channel. when several channels are enabled, the contents of the status register should be attached to the 24 - bit word allowing the user to ide ntify the channel that corresponds to each conversion. the four lsbs of the status register indicate the channel to which the conversion corresponds. table 23 and table 24 show the channel options for dif ferential mode and pseudo differential mode with the corresponding channel id values in the status register. to attach the status register value to the conversion, bit dat_sta in the mode register should be set to 1. when several channels are enabled, th e adc allows the complete filter settling time to generate a valid conversion each time the channel is ch anged. the AD7193 automatically takes care of this through the following sequence: 1. when a channel is selected, the modulator and filter are reset. 2. th e AD7193 allows the complete settling time to generate a valid conversion. 3. dout/ rdy indicates when a valid conversion is available . 4. the AD7193 selects the next enabled channel and converts on that channel. 5. the user can read the da ta register while the adc is performing the conversion on the next channel. the time required to read a valid conversion from all enabled channels is equal to t settle number of enabled channels for example, if the sinc 4 filter is selected, chop is disab led, and zero latency is disabled, the settling time for each channel equals t settle = 4/ f adc where f adc is the output data rate when continuously converting on a single channel. therefore, the time required to read all enabled channels is (4 number of enabled channels) / f adc rdy conversions channel a channel b 1/f adc channel c 08367-060 figure 24 . channel sequencer digital interface as indicated in the on - chip registers section, the programmable functions of the AD7193 are controlled using a set of on - chip registers. data is written to these registers via the serial interface of the part. read access to the on - chip registers is also provided by this interface. all communication with the part must start with a write to the communications regis ter. after power - on or reset, the device expects a write to its communications register. the data written to this register determines whether the next operation is a read operation or a write operation, and it determines to which register this read or writ e operation occurs. therefore, write access to any of the other registers on the part begins with a write operation to the communications register, followed by a write to the selected register. a read operation from any other register (except when continuo us read mode is selected) starts with a write to the communications register, followed by a read operation from the selected register. the serial interface of the AD7193 consists of four signals: cs , din, sclk, and dout/ rdy . the din line is used to transfer data into the on - chip registers and dout/ rdy is used for accessing data from the on - chip registers. sclk is the serial clock input for the device, and all data transfers (either on din or dout/ rdy ) occur with respect to the sclk signal. the dout/ rdy pin also functions as a data - ready signal, the line going low when a new data - word is available in the output register. it is reset high when a read operation from the data register is complete. it also goes high prior to the updating of the data register to indicate when not to read from the device, to ensure that a data read is not attempted while the register is being updated. cs is used to select a device. it can be used to decode the AD7193 in systems where several components are connected to the serial bus. figure 3 and figure 4 show timing diagrams for interf acing to the AD7193 using cs to decode the part. figure 3 shows the timing for a read operation from the output shift register of the AD7193, and figure 4 shows the timing for a write operation to the input shift register. it is possible to read the same word from the data register several times even though the dout/ rdy line returns high after the first read operation. however, care must be taken to ensur e that the read operations are completed before the next output update occurs. in continuous read mode, the data register can be read only once. the serial interface can operate in 3 - wire mode by tying cs low. in this case, the sclk , din, and dout/ rdy lines are used to communicate with the AD7193. the end of the conversion can be monitored using the rdy bit or pin. this scheme is suitable for interfaci ng to microcontrollers. if cs is required as a decoding signal, it can be generated from a port pin. for microcontroller interfaces, it is recommended that sclk idle high between data transfers.
data sheet AD7193 rev. d | page 35 of 56 the AD7193 can be operated with cs used as a frame synchro - nization signal. this scheme is useful for dsp interfaces. in this case, the first bit (msb) is effectively clocked out by cs because cs normally occurs after the falling edge of sclk in dsps. the sclk can continue to run between data transfers, provided the timing numbers are obeyed. the serial interface can be reset by writing a series of 1s to the din input. if a logic 1 is written to the AD7193 din line for at least 40 serial clock cycles, the seri al interface is reset. this ensures that the interface can be reset to a known stat e if the interface i s lost due to a software error or a glitch in the system. reset returns the interface to the state in which it expects a write to the communications regi ster. this operation resets the contents of all registers to their power - on values. following a reset, the user should allow a period of 500 s before addressing the serial interface. the AD7193 can be configured to continuously convert or to perform a si ngle conversion (see figure 25 through figure 27) . single conversion mode in single conversion mode, the AD7193 is placed in power - down mode after conversions. when a single conversion is initiated by se tting md2 to 0 , md1 to 0, and md0 to 1 in the mode register, the AD7193 powers up, performs a single conversion, and then returns to power - down mode. the on - chip oscillator requires 1 ms, approximately, to power up. dout/ rdy goes l ow to indicate the completion of a conversion . when the data - word has been read from the data register, dout/ rdy goes high. if cs is low, dout/ rdy remains high until another conversion is initiated and completed. the data register can be read several times, if required, even when dout/ rdy has gone high. if several channels are enabled, the adc sequences through the enabled channels and performs a conversion on each c hannel. when a conversion is started, dout/ rdy goes high and remains high until a valid conversion is available. as soon as the conversion is available, dout/ rdy goes low. the adc then selects the next channel and begins a conversion. the user can read the present conversion while the next conversion is being performed. as soon as the next conversion is complete, the data register is updated; therefore, the user has a limited period in which to read the conversi on. when the adc has performed a single conversion on each of the selected channels, it returns to power - down mode. if the dat_sta bit in the mode register is set to 1, the contents of the status register are output along with the conversion each time that the data read is performed. the four lsbs of the status register indicate the channel to which the conversion corresponds . din sclk dout/rdy cs 0x08 0x58 data 0x280060 08367-061 figure 25 . single conversion
AD7193 data sheet rev. d | page 36 of 56 continuous conversion mode continuous conversion is the default power - up mode. the AD7193 converts continuously, and the rdy bit in the status register goes low each time a conversion is complete. if cs is low, the dout/ rdy line also goes low when a convers ion is completed. to read a conversion, the user writes to the commu - nications register, indicating that the next operation is a read of the data register. when the data - word has been read from the data register, dout/ rdy goes high. the user can read this register additional times, if required. however, the user must ensure that the data register is not being accessed at the completion of the next conversion or else the new conversion word is lost. when several channels are enabled, t he adc continuously loops through the enabled channels, performing one conversion on each channel per loop. the data register is updated as soon as each conversion is available. the dout/ rdy pin pulses low each time a conversion is a vailable. the user can then read the c onversion while the adc converts on the next enabled channel . if the dat_sta bit in the mode register is set to 1, the contents of the status register are output along with the conversion each time that the data read i s performed. the status register indicates the channel to which the conversion corresponds. din sclk dout/rdy cs 0x58 0x58 data data 08367-062 figure 26 . continuous conversion
data sheet AD7193 rev. d | page 37 of 56 continuous read rather than write to the communications register each time a conversion is complet e to access the data, the AD7193 can be configured so that the conversions are placed on the dout/ rdy line automatically. by writing 01011100 to the communi - cations regist er, the user need only apply the appropriate number of sclk c ycles to the adc, and the conversion word is auto - matically placed on the dout/ rdy line when a conversion is complete. the adc should be configured for continuous conversion mode. when dout/ rdy goes lo w to ind icate the end of a conversion , sufficient sclk cycles must be applied to the adc; the data conversion is then placed on the dout/ rdy line. when the conversion is read, dout/ rdy returns high until the next conve rsion is available. in this mode, the data can be read only once. t he user must also ensure that the data - word is read before the next conversion is complete. if the user has not read the conversion before the completion of the next conversion, or if insuf ficient serial clocks are applied to the AD7193 to read the word, the serial output register is reset when the next conversion is complete, and the new conversion is placed in the output serial register. to exit the continuous read mode, instruction 0101 1000 must be written to the communications register while the rdy pin is low. while in the continuous read mode, the adc monitors activity on the din line so that it can receive the instruction to exit the continuous read mode. addi tionally, a reset occurs if 40 consecutive 1s are seen on din. therefore, din should be held l ow in continuous read mode until an instruction is to be written to the device. when several channels are enabled, the adc continuously steps through the enabled channels and performs one conversion on each channel each time that it is selected. dout/ rdy pulses low when a conversion is available. when the user applies sufficient sclk pulses, the data is automatically placed on the dout/ rdy pin. if the dat_sta bit in the mode register is set to 1, the contents of the status register are output along with the conversion. the status register indicates the channel to which the conversion corresponds. din sclk dout/rdy cs 0x5c data data data 08367-063 figure 27 . continuous read
AD7193 data sheet rev. d | page 38 of 56 reset the circuitry and serial interface of the AD7193 can be reset by writing consecutive 1s to the device; 40 consecutive 1s are required to perform the reset. this resets the logic, the digital filter, and the analog modulator, whereas all on - chip registers are reset to their default values. a reset is automatically performed on power - up. when a reset is initiated, the user must allow a period of 500 s before accessing any of the on - chip registers. a reset is useful i f the serial interface loses synchronization due to noise on the sclk line. system synchronizati on the sync input allows the user to reset the modulator and the digital filter without affecting any of the setup conditions on the part . this allows the user to start gathering samples of the analog input from a known point in time, that is, the rising edge of sync . sync needs to be taken low for at least four master clock cycles to implement the synchronization function. if multiple AD7193 devices are operated from a common master clock, they can be synchronized so that their data registers are updated simultaneously. a falling edge on the sync pin resets the digital fi lter and the analog modulator and places the AD7193 into a consistent, known state. while the sync pin is low, the AD7193 is maintained in this state. on the sync rising edge, the modulator and filter are taken out of this reset state and, on the next clock edge, the part starts to gather input samples again. in a system using multiple AD7193 devices , a common signal to their sync pins synchronizes their operation. this is normally done after each AD7193 has performed its own calibration or has calibration coefficients loaded into its calibration registers. the conversions from the AD7193s are then synchronized. the part is taken out of reset on the master clock falling edge following t he sync low - to - high transition. therefore, when multiple devices are being synchronized, the sync pin should be taken high on the master clock rising edge to ensure that all devices begin sampling on the master clock falling edge. if the sync pin is not taken high in sufficient time, it is possible to have a difference of one master clock cycle between the devices; that is, the instant at which conversions are available differs from part t o part by a maximum of one master clock cycle. the sync pin can also be used as a start conversion command. in this mode, the rising edge of sync starts conversion, and the falling edge of r dy indicates when the conversion is complete. the settling time of the filter has to be allowed for each data register update. for example, if the adc is configured to use the sinc 4 filter, zero latency is disabled, and chop is disabled , t he settling ti me equals 4/f adc , where f adc is the output data rate when continuously converting on a single channel. enable parity when the enpar bit in the mode register is set to 1, parity is enabled. the contents of the status register must be transmitted along with each 24 - bit conversion when the parity function is enabled. to append the contents of the status register to each conversion read, the dat_sta bit in the mode register should be set to 1. for each conversion read, the parity bit in the status register is programmed so that the overall number of 1s trans - mitted in the 24 - bit data - word is even. therefore, for example, if the 24 - bit conversion contains 11 ones (binary format), the parity bit is set to 1 so that the total number of 1 s in the serial transmissio n is even. if the microprocessor receives an odd number of 1 s, it knows that the data received has been corrupted. the parity function does not ensure that all errors are detected. for example, two bits of corrupt data can result in the micro - processor rec eiving an even number of 1 s. therefore, an error condition is not detected. clock the AD7193 includes an i nternal 4.92 mhz clock on chip. this internal clock has a tolerance of 4%. either the internal clock or an external crystal/clock can be used as the clock source to the AD7193. the clock source is selected using the clk1 and clk0 bits in the mode register. when an external crystal is used, it must be connected across the mclk1 and mclk2 pins. the crystal manufacturer recommends the load capacitances required for the crystal. the mclk1 and mclk2 pins of the AD7193 have a capacitance of 15 pf, typically. if an external clock source is used, the clock source must be connected to the mclk2 pin, and the mclk1 pin can remain floating. the internal clock ca n also be made available at the mclk2 pin. this is useful when several adcs are used in an application and the devices must be synchronized. the internal clock from one device can be used as the clock source for all adcs in the system. using a common clock , the devices can be synchronized by applying a common reset to all devices, or the sync pin can be pulsed. bridge power - down switch in bridge applications such as strain gages and load cells, the bridge itself consumes the majority of the current in the system. for example, a 350 load cell requires 15 ma of current when excited with a 5 v supply. to minimize the current consumption of the system, the bridge can be disconnected (when it is not being used) using the bridge power - dow n switch. figure 22 shows how the bridge power - down switch is used. the switch can withstand 30 ma of continuous current, and it has an on resistance of 1 0 maximum.
data sheet AD7193 rev. d | page 39 of 56 temperature sensor embedded in the AD7193 is a temperature s ensor. this is selected using the temp bit in the configuration register. when the temp bit is set to 1, the temperature sensor is enabled. when the temperature sensor is selected and bipolar mode is selected, the device should return a code of 0x800000 wh en the temperature is 0 kelvin, theoretically. a one - point calibration is needed to obtain the optimum performance from the sensor. therefore, a conversion at 25c should be recorded and the sensitivity calculated. the sensitivity is 2815 codes/c, approxi mately. the equation for the temperature sensor is temperature (k) = ( conversion ? 0x800000)/2815 k temperature (c) = temperature (k) ? 273 following the one - point calibration, the internal temperature sensor has an accuracy of 2c, typically. logic out puts the AD7193 has four general - purpose digital outputs : p0, p1, p2, and p3. these are enabled using the gp32en and gp10en bits in the gpocon register. the pins can be pulled high or low using the p0dat to p3dat bits in the gpocon register; that is, the v alue at the pin is determined by the setting of the p0dat to p3dat bits. the logic levels for these pins are deter - mined by av dd rather than by dv dd . when the gpocon register is read, bit p0dat to bit p3dat reflect the actual value at the pins; this is us eful for short - circuit detection. these pins can be used to drive external circuitry, for example, an external multiplexer. if an external multiplexer is used to increase the channel count, the multiplexer logic pins can be controlled via the AD7193 genera l- purpose output pins. the general - purpose output pins can be used to select the active multiplexer pin. because the operation of the multiplexer is independent of the AD7193, the AD7193 modulator and filter should be reset using the sy nc pin or by a write to the mode or configuration register each time that the multiplexer channel is changed. calibration the AD7193 provides four calibration modes that can be programmed via the mode bits in the mode register. these modes are internal zero - scale calibration, internal full - scale calibration, system zero - scale calibration, and system full - scale calibration. a calibration can be performed at any time by setting the md2 to md0 bits in the mode register appropriately. a calibration should b e performed when the gain is changed. after each conversion, the adc conversion result is scaled using the adc calibration registers before being written to the data register. the offset calibration coefficient is subtracted from the result prior to multip lication by the full - scale coefficient. to start a calibration, write the relevant value to the md2 to md0 bits. the dout/ rdy pin and the rdy bit in the status register go high when the calibration initiates . when the calibration is complete, the contents of the corresponding calibration registers are updated, the rdy bit in the status register is reset, the dout/ rdy pin returns low (if cs i s low), and the AD7193 reverts to idle mode. during an internal zero - scale or full - scale calibration, the respective zero input and full - scale input are automatically connected internally to the adc input pins. a system calibration, however, expects the sy stem zero - scale and system full - scale voltages to be applied to the adc pins before initiating the calibration mode. in this way, errors external to the adc are removed. from an operational point of view, treat a calibration like another adc conversion. a zero - scale calibration, if required, must always be performed before a full - scale calibration. set the system software to monitor the rdy bit in the status register or the dout/ rdy pin to determine the end of calibration via a polling sequence or an interrupt - driven routine. with chop disabled, both an internal zero - scale calibration and a system zero - scale calibration require a time equal to the settling time, t settle (4/f adc for the sinc 4 filter and 3/f adc fo r the sinc 3 filter). with chop enabled, an internal zero - scale calibration is not needed because the adc itself minimizes the offset continuously. however, if an internal zero - scale calibration is performed, the settling time, t settle (2/f adc ), is required to perform the calibration. similarly, a system zero - scale calibration requires a time of t settle to complete. to perform an internal full - scale calibration, a full - scale input voltage is automatically connected to the selected analog input for this cali bration. for a gain of 1, the time required for an internal full - scale calibration is equal to t settle . for higher gains, the internal full - scale calibration requires a time of 2 t settle . a full - scale calibration is recommended each time the gain of a c hannel is changed to minimize the full - scale error. a system full - scale calibration requires a time of t settle . with chop disabled, the zero - scale calibration (internal or system zero - scale) should be performed before the system full - scale calibration is i nitiated. an internal zero - scale calibration, system zero - scale calibration, and system full - scale calibration can be performed at any output data rate. an internal full - scale calibration can be performed at a ny output data rate for which the filter word, fs[9:0], is divisible by 16, fs[9:0] being the decimal equivalent of the 10 - bit word written to bit fs9 to bit fs0 in the mode register. therefore, internal full - scale calibrations can be performed at output data rates such as 10 hz or 50 hz when chop is d isabled. using these lower output data rates , results in better calibration accuracy.
AD7193 data sheet rev. d | page 40 of 56 the offset error is, typically, 150 v /gain. if the gain is changed, it is advisable to perform a calibration. a zero - scale calibration (an internal zero - scale calibra tion or a system zero - scale calibration) reduces the offset error to the order of the noise. the gain error of the AD7193 is factory calibrated at a gain of 1 with a 5 v power supply at ambient temperature. following this calibration, the gain error is , ty pically, 0.001% a t 5 v. table 27 shows the typical uncalibrated gain error for the different gain settings. table 27 . typical precalibration gain error vs. gain gain precalibration gain error (%) 8 ?0.11 16 ?0.20 32 ?0.23 64 ?0.29 128 ?0.39 an internal full - scale calibration reduces the gain error to 0.001%, typically, when the gain is equal to 1. for hi gher gains, the gain error post internal full - scale calibration is 0.003%, typically , when av dd is equal to or higher than 4.7 5 v. w h e n av dd is less than 4.75 v, the gain error after internal full - scale calibration is 0.005%, typically. whe n av dd is less than 4.75 v, the clk_div bit must be set when performing internal full - scale calibrations. this increases the calib ration time by a factor of 2. the accuracy of the internal full - scale calibration is further increased if chop is enabled and a low output data rate is used while performing the calibration. a system full - scale calibration reduces t he gain error to the order of the noise irrespective of the analog power supply voltage. the AD7193 gives the user access to the on - chip calibration registers, allowing the microprocessor to read the calibration coefficients of the device and also to write its own calibration coefficients from prestored values in the eeprom. a read of the registers can be performed at any time. however, the adc must be placed in power - down or idle mode when writing to the registers. the values in the calibration registers a re 24 bits wide. the span and offset of the part can also be manipulated using the registers.
data sheet AD7193 rev. d | page 41 of 56 digital filter the AD7193 offers a lot of flexibility in the digital filter. the device has five filter options. the device can be operated with a sinc 3 or sinc 4 filter, chop can be enabled or disabled, and zero latency can be enabled. finally, an averaging block can be included after the sinc filter, which gives a fast settling mode. the option selected affects the output data rate, settling time, and 50 hz/60 hz rejection. the following sections describe each filter type, indicating the available output data rates for each filter option. the filter response, along with the settling time and 50 hz/60 hz rejection, is also discussed. sinc 4 filter (chop disabled) when the AD7193 is powered up, the sinc 4 filter is selected by default and chop is disabled. this filter gives excellent noise performance over the complete range of output data rates. it also gives the best 50 hz/60 hz rejection, but it has a long settling time. sinc 3 / sinc 4 post filter modulator adc chop 08367-024 figure 28. sinc 4 filter (chop disabled) sinc 4 output data rate/settling time the output data rate (the rate at which conversions are available on a single channel when the adc is continuously converting) is equal to f adc = f clk /(1024 fs[9:0] ) where: f adc is the output data rate. f clk is the master clock (4.92 mhz nominal). fs[9:0] is the decimal equivalent of bit fs9 to bit fs0 in the mode register. the output data rate can be programmed from 4.7 hz to 4800 hz; that is, fs[9:0] can have a value from 1 to 1023. the settling time for the sinc 4 filter is equal to t settle = 4/ f adc when a channel change occurs, the modulator and filter are reset. the settling time is allowed to generate the first conver- sion after the channel change. subsequent conversions on this channel occur at 1/f adc . channel conversions channel a ch a ch a ch a ch b ch b ch b channel b 1/ f adc 0 8367-025 figure 29. sinc 4 channel change when conversions are performed on a single channel and a step change occurs, the adc does not detect the change in analog input. therefore, it continues to output conversions at the pro- grammed output data rate. however, it is at least four conversions later before the output data accurately reflect the analog input. if the step change occurs while the adc is processing a conver- sion, then the adc takes five conversions after the step change to generate a fully settled result. 1/ f adc analog input adc output fully settled 08367-026 figure 30. asynchronous step change in analog input the 3 db frequency for the sinc 4 filter is equal to f 3db = 0.23 f adc table 28 gives some examples of the relationship between the values in bits fs[9:0] and the corresponding output data rate and settling time. table 28. examples of output data rates and the corresponding settling time fs[9:0] output data rate (hz) settling time (ms) 480 10 400 96 50 80 80 60 66.6 sinc 4 zero latency zero latency is enabled by setting the single bit (bit 11) in the mode register to 1. with zero latency, the complete settling time is allowed for each conversion. therefore, the conversion time when converting on a single channel or when converting on several channels is constant. the user does not need to consider the effects of channel changes on the output data rate. when the channel sequencer is enabled, the AD7193 automatically operates in zero latency mode. the output data rate equals f adc = 1/ t settle = f clk /(4 1024 fs[9:0] ) where: f adc is the output data rate. f clk is the master clock (4.92 mhz nominal). fs[9:0] is the decimal equivalent of bit fs9 to bit fs0 in the mode register.
AD7193 data sheet rev. d | page 42 of 56 when the analog input is constant or a channel change occurs, valid conversions are available at a constant output data rate. when conversions are being performed on a single channel and a step change occurs on the analog input, the adc continues to output full y settled conversions if the step change is synchronized with the conversion process. if the step change is asynchronous, one conversion is output from the adc , w hich is not completely settled (see figure 31). analog input adc output fully settled 1/ f adc 08367-027 figure 31 . sinc 4 zero latency operation table 29 shows examples of output data rate and the corresponding fs values. table 29 . exampl es of output data rates and the corresponding settling time (zero latency) fs[9: 0 ] output data rate (hz) settling time (ms) 480 2.5 400 96 12.5 80 80 15 66.6 sinc 4 50 hz/60 hz rejection figure 32 shows the frequency respo nse of the sinc 4 filter when fs[9:0] is set to 9 6 and the master clock is 4.92 mhz . with zero latency disabled, the output data rate is equal to 50 hz. with zero latency enabled, the output data rate is 12.5 hz. the sinc 4 filter provides 50 hz (1 hz) reje ction in excess of 120 db minimum , assuming a stable master clock. ?120 ?1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 25 50 75 100 125 150 frequenc y (hz) fi l ter gain (db) 08367-028 figure 32 . sinc 4 filter response ( fs[9:0] = 96 ) figure 33 shows the frequency response when fs[9:0] is programmed to 80 and the master clock is equal to 4.92 mhz . the output data rate is 60 hz when zero latency is disabled and 15 hz when zero latency is enabled. the sinc 4 filter provides 6 0 hz (1 hz) rejection of 120 db minimum , assuming a stable master clock . ?120 ?1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 30 60 90 120 150 frequenc y (hz) fi l ter gain (db) 08367-029 figure 33 . sinc 4 filter response ( fs[9:0] = 80 ) simultaneous 50 hz and 60 hz r ejection is obtained when fs[9:0] is programmed to 480 and the master clock equals 4.92 mhz . the output data rate is 10 hz when zero latency is disabled and 2.5 hz when zero la tency is enabled. the sinc 4 filter provides 50 hz (1 hz) and 60 hz (1 hz) rejection of 120 db minimum , assuming a stable master clock. ?120 ? 1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 30 60 90 120 150 frequenc y (hz) fi l ter gain (db) 08367-030 figure 34 . sinc 4 filter response (fs[9:0] = 480)
data sheet AD7193 rev. d | page 43 of 56 simultaneous 50 hz/60 hz rejection can also be achieved using the rej60 bit in the mode register. when fs[9:0] is set to 96 and rej60 is set to 1, notches are placed at 50 hz and 60 hz. the output data rate is 50 hz when zero latency is disabled and 12.5 hz when zero latency is enabled. figure 35 shows the frequency response of the sinc 4 filter. the filter provides 50 hz 1 hz and 60 hz 1 hz rejection of 82 db minimum, assuming a stable 4.92 mhz master clock. ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 25 50 75 100 125 150 frequency (hz) filter gain (db) 08367-031 figure 35. sinc 4 filter response (fs[9:0] = 96, rej60 = 1) sinc 3 filter (chop disabled) a sinc 3 filter can be used instead of the sinc 4 filter. the filter is selected using the sinc3 bit in the mode register. the sinc 3 filter is selected when the sinc3 bit is set to 1. this filter has good noise performance when operating with output data rates up to 1 khz. it has moderate settling time and moderate 50 hz/60 hz (1 hz) rejection. sinc 3 /sinc 4 post filter modulator adc chop 08367-032 figure 36. sinc 3 filter (chop disabled) sinc 3 output data rate and settling time the output data rate (the rate at which conversions are available on a single channel when the adc is continuously converting) is equal to f adc = f clk /(1024 fs[9:0] ) where: f adc is the output data rate. f clk is the master clock (4.92 mhz nominal). fs[9:0] is the decimal equivalent of bit fs9 to bit fs0 in the mode register. the output data rate can be programmed from 4.7 hz to 4800 hz; that is, fs[9:0] can have a value from 1 to 1023. the settling time is equal to t settle = 3/ f adc the 3 db frequency is equal to f 3db = 0.272 f adc table 30 gives some examples of fs settings and the corresponding output data rates and settling times. table 30. examples of output data rates and the corresponding settling time fs[9:0] output data rate (hz) settling time (ms) 480 10 300 96 50 60 80 60 50 when a channel change occurs, the modulator and filter reset. the complete settling time is allowed to generate the first conversion after the channel change (see figure 37). subsequent conversions on this channel are available at 1/f adc . channel conversions channel a ch a ch a ch a ch b ch b ch b ch b channel b 1/ f adc 0 8367-033 figure 37. sinc 3 channel change when conversions are performed on a single channel and a step change occurs, the adc does not detect the change in analog input. therefore, it continues to output conversions at the programmed output data rate. however, it is at least three conversions later before the output data accurately reflects the analog input. if the step change occurs while the adc is processing a conversion, the adc takes four conversions after the step change to generate a fully settled result. 1/ f adc analog input adc output fully settled 08367-034 figure 38. asynchronous step change in analog input
AD7193 data sheet rev. d | page 44 of 56 sinc 3 zero latency zero latency is enabled by setting the single bit (bit 11) in the mode register to 1. with zero latency, the complete settling time is allowed for each conversion. therefore, the conversion time when converting on a single channel or when converti ng on several channels is constant. t he user does not need to consider the effects of channel changes on the output data rate. when the channel sequencer is enabled, the AD7193 automatically operates in zero latency mode. the output data rate equals f adc = 1/ t settle = f clk /(3 1024 fs[9:0] ) where: f adc is the output data rate. f clk is the master clock (4.92 mhz nominal). fs[9:0] is the decimal equivalent of bit fs9 to bit fs0 in the mode register. when the analog input is constant or a channel change occurs, valid conversions are available at a constant output data rate. when conversions are being performed on a single channel and a step change occurs on the analog input, the adc continues to output fully set tled conversions if the step change is synch ronized with the conversion process. if the step change is asynchronous, one conversion is output from the adc that is not completely settled (see figure 39) . analog input adc output fully settled 1/ f adc 08367-035 figure 39 . sinc 3 zero latency operation table 31 provides examples of output data rate s and the corresponding fs values. table 31 . examples of output data rates and the corresponding settling time (zero latency) fs[9:0] output data rate (hz) settling time (ms) 480 3.3 300 96 16.7 60 80 20 50 sinc 3 50 hz/60 hz rejection figure 40 show the frequency response of the sinc 3 filter when fs[9:0] is set to 96 and the master clock equals 4.92 mhz . the output data rate is eq ual to 50 hz when zero latency is disabled and 16.7 hz when zero latency is enabled. the sinc 3 filter gives 50 hz 1 hz rej ection of 95 db minimum for a stable master clock. ?120 ? 1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 25 50 75 100 125 150 frequenc y (hz) fi l ter gain (db) 08367-036 figure 40 . sinc 3 filter response ( fs[9:0] = 96 ) when fs[9:0] is set to 80 and the master clock equals 4.92 mhz , 60 hz rejection is achieved (see figure 41 ). the output dat a rate is equal to 60 hz when zero latency is disabled and 20 hz when zero latency is enabled. the sinc 3 filter has rejection of 95 db minimum at 60 hz 1 hz , assuming a stable master clock . ?120 ? 1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 30 60 90 120 150 frequenc y (hz) fi l ter gain (db) 08367-037 figure 41 . sinc 3 filter response (fs[9:0] = 80)
data sheet AD7193 rev. d | page 45 of 56 simultaneous 50 hz and 60 hz rejection is obtained when fs[9:0] is set to 480 (master clock = 4.92 m hz) , as shown in figure 42 . the output data rate is 10 hz when zero latency is disabled and 3.3 hz when zero latency is enabled. the sinc 3 fil ter has rejection of 100 db minimum at 50 hz 1 hz and 60 hz 1 hz . ?120 ? 1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 30 60 90 120 150 frequenc y (hz) fi l ter gain (db) 08367-038 figure 42 . sinc 3 filter response (fs[9:0] = 480) simultaneous 50 hz/60 hz rejection is also achieved using the rej60 bit in the mode register. when fs[9:0] is programmed to 96 and the rej60 bit is set to 1, notches are placed at both 50 hz and 60 hz for a stable 4.92 mhz master clock . figure 43 shows the frequency response of the sinc 3 filter with this configuration . assuming a stable clock, the rejection at 50 hz/ 60 hz (1 hz) i s in excess of 67 db minimum . ?120 ? 1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 25 50 75 100 125 150 frequenc y (hz) fi l ter gain (db) 08367-039 figure 43 . sinc 3 filter response (fs[9:0] = 96 , rej60 = 1) chop enabled (sinc 4 filter) with chop enabled, the adc offset and offset drift are mi nimized . t he analog input pins are continuously swapped. w ith the analog input pins connected in o ne direction, the settling time of the sin c filter is allowed and a conversion is recorded . the analog input pins are then inverted , and another settled conversion is obtained. subsequent conve rsions are averaged to minimize the offset. this continuous swa pping of the analog input pins and the averaging of subsequent conversions means that the offset drift is also minimized. with chop enabled, the resolution increases by 0.5 bits. sinc 3 / sinc 4 post filter modulator adc chop 08367-040 figure 44 . chop enabled output data rate and settl ing time (sinc 4 chop enabled) for the s inc 4 filter , the output data rate is equal to f adc = f clk /(4 1024 fs[9:0] ) where: f adc is the output data rate. f clk is the master clock (4.92 mhz nominal). fs[9:0] is the decimal equivalent of b it fs9 to bit fs0 in the mode register. the value of fs[9:0] can be varied from 1 to 1023. this results in an output d ata rate of 1.1 7 hz to 1200 hz. the settling time is equal to t settle = 2/ f adc table 32 gives some examples of fs [ 9:0] values and the corresponding output data rates and settling times. table 32 . examples of output data rates and the corresponding settling time fs[9:0] output data rate (hz) settling time (ms) 96 12.5 160 80 15 133
AD7193 data sheet rev. d | page 46 of 56 when a channel change occurs, the modulator and filter reset. the complete settling time is required to generate the first conversion after the channel change. subsequent conversions on this channel occur at 1/f adc . channel conversions channel a ch a ch a ch a ch b ch b ch b ch b channel b 1/ f adc ch b 0 8367-041 figure 45. channel change (sinc 4 chop enabled) when conversions are performed on a single channel and a step change occurs, the adc does not detect the change in analog input; therefore, it continues to output conversions at the programmed output data rate. however, it is at least two conversions later before the output data accurately reflects the analog input. if the step change occurs while the adc is processing a conversion, the adc takes three conversions after the step change to generate a fully settled result. 1/ f adc analog input adc output fully settled 08367-042 figure 46. asynchronous step change in analog input (sinc 4 chop enabled) the cutoff frequency f 3db is equal to f 3db = 0.24 f adc 50 hz/60 hz rejection (sinc 4 chop enabled) when fs[9:0] is set to 96 and chopping is enabled, the output data rate is equal to 12.5 hz for a 4.92 mhz master clock. the filter response shown in figure 47 is obtained. the chopping introduces notches at odd integer multiples of f adc /2. the notches due to the sinc filter in addition to the notches introduced by the chopping mean that simultaneous 50 hz and 60 hz rejection is achieved for an output data rate of 12.5 hz. the rejection at 50 hz/60 hz 1 hz is typically 63 db, assuming a stable master clock. ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 25 50 75 100 125 150 frequency (hz) filter gain (db) 0 8367-043 figure 47. sinc 4 filter response (fs[9:0] = 96, chop enabled) the 50 hz/60 hz rejection can be improved by setting the rej60 bit in the mode register to 1. with fs[9:0] set to 96 and rej60 set to 1, the filter response shown in figure 48 is achieved. the output data rate is unchanged but the 50 hz/ 60 hz (1 hz) rejection is increased to 83 db typically. ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 255075100125150 frequency (hz) filter gain (db) 08367-044 figure 48. sinc 4 filter response (fs[9:0] = 96, chop enabled, rej60 = 1)
data sheet AD7193 rev. d | page 47 of 56 chop enabled (sinc 3 filter) with chop enabled, the adc offset and offset drift are minimized. the analog input pins are continuously swapped. with the analog input pins connected in one direction, the settling time of the sinc filter is allowed and a conversion is recorded. the analog input pins invert and another settled conversion is obtained. subsequent conversions are averaged to minimize the offset. this continuous swapping of the analog input pins and the averaging of subsequent conversions means that the offset drift is also minimized. with chop enabled, the resolution increases by 0.5 bits. using the sinc 3 filter with chop enabled is suitable for output data rates up to 320 hz. sinc 3 / sinc 4 post filter modulator adc chop 08367-045 figure 49. chop enabled (sinc 3 chop enabled) output data rate and settling time (sinc 3 chop enabled) for the sinc 3 filter, the output data rate is equal to f adc = f clk /(3 1024 fs[9:0] ) where: f adc is the output data rate. f clk is the master clock (4.92 mhz nominal). fs[9:0] is the decimal equivalent of bit fs9 to bit fs0 in the mode register. the value of fs[9:0] can be varied from 1 to 1023. this results in an output data rate of 1.56 hz to 1600 hz. the settling time is equal to t settle = 2/ f adc table 33. examples of output data rates and the corresponding settling time (chop enabled, sinc 3 filter) fs[9:0] output data rate (hz) settling time (ms) 96 16.7 120 80 20 100 when a channel change occurs, the modulator and filter are reset. the complete settling time is required to generate the first conversion after the channel change. subsequent conversions on this channel occur at 1/f adc . channel conversions channel a ch a ch a ch a ch b ch b ch b ch b channel b 1/ f adc ch b 0 8367-046 figure 50. channel change (sinc 3 chop enable) if conversions are performed on a single channel and a step change occurs, the adc does not detect the change in analog input; therefore, it continues to output conversions at the programmed output data rate. however, it is at least two conversions later before the output data accurately reflects the analog input. if the step change occurs while the adc is processing a conversion, then the adc takes three conversions after the step change to generate a fully settled result. 1/ f adc analog input adc output fully settled 08367-047 figure 51. asynchronous step change in analog input (sinc 3 chop enabled) the cutoff frequency f 3db is equal to f 3db = 0.24 f adc 50 hz/60 hz rejection (sinc 3 chop enabled) when fs[9:0] is set to 96 and chopping is enabled, the filter response shown in figure 52 is obtained. the output data rate is equal to 16.7 hz for a 4.92 mhz master clock. the chopping introduces notches at odd integer multiples of f adc /2. the notches due to the sinc filter in addition to the notches introduced by the chopping means that simultaneous 50 hz and 60 hz rejection is achieved for an output data rate of 16.7 hz. the rejection at 50 hz/60 hz 1 hz is typically 53 db, assuming a stable master clock. ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 25 50 75 100 125 150 frequency (hz) filter gain (db) 08367-048 figure 52. sinc 3 filter response (fs[9:0] = 96, chop enabled)
AD7193 data sheet rev. d | page 48 of 56 the 50 hz/60 hz rejection can be improved by setting the rej60 bit in the mode register to 1. with fs[9:0] set to 96 and rej60 set to 1, the filter response shown in figure 53 is achieved. the output data rate is unchanged but the 50 hz/60 hz 1 hz rejection improves to 73 db typically. ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 25 50 75 100 125 150 frequency (hz) filter gain (db) 08367-049 figure 53. sinc 3 filter response (fs[9:0] = 96, chop enabled, rej60 = 1) fast settling mode (sinc 4 filter) in fast settling mode, the settling time is close to the inverse of the first filter notch; therefore, the user can achieve 50 hz and/or 60 hz rejection at an output data rate close to 1/50 hz or 1/60 hz. the settling time is equal to 1/output data rate. therefore, the conversion time is constant when converting on a single channel or when converting on several channels. there is no added latency when switching channels. enable the fast settling mode using bit avg1 and bit avg0 in the mode register. in fast settling mode, a postfilter is included after the sinc 4 filter. the postfilter averages by 2, 8, or 16, depending on the settings of the avg1 and avg0 bits. sinc 3 / sinc 4 post filter modulator adc chop 08367-050 figure 54. fast settling mode, sinc 4 filter output data rate and settling time, sinc 4 filter with chop disabled, the output data rate is f adc = f clk /((4 + av g ? 1) 1024 fs[9:0] ) (1) f adc is the output data rate. f clk is the master clock (4.92 mhz nominal). avg is the average. fs[9:0] is the decimal equivalent of bit fs9 to bit fs0 in the mode register. if avg1 = avg0 = 0, the fast settling mode is not enabled. in this case, equation 1 is not relevant. the settling time is equal to t settle = 1/ f adc table 34 lists sample fs words and the corresponding output data rates and settling times. table 34. examples of output data rates and the corresponding settling time (fast settling mode, sinc 4 ) fs[9:0] average output data rate (hz) settling time (ms) 96 16 2.63 380 30 16 8.4 118.75 6 16 42.1 23.75 5 16 50.53 19.79 when the analog input channel is changed, there is no additional delay in generating valid conversionsthe device functions as a zero latency adc. channel conversions channel a ch a ch a ch a ch b ch b ch b ch b channel b 1/ f adc ch b ch b 0 8367-051 figure 55. fast settling, sinc 4 filter when the device is converting on a single channel and a step change occurs on the analog input, the adc does not detect the change and continues to output conversions. if the step change is synchronized with the conversion, only fully settled results are output from the adc. however, if the step change is asyn- chronous to the conversion process, there is one intermediate result, which is not completely settled (see figure 56). analog input adc output valid 1/ f adc 0 8367-052 figure 56. step change on analog input, sinc 4 filter the output data rate is the same for chop enabled and chop disabled in fast settling mode. however, when chop is enabled, the settling time equals t settle = 2/ f adc therefore, if chop is enabled, the sinc 4 filter is selected, fs[9:0] is set to 6, and averaging by 16 is enabled. the output data rate is equal to 42.1 hz when the master clock equals 4.92 mhz. therefore, the conversion time equals 1/42.10 hz or 23.75 ms and the settling time is equal to 47.5 ms.
data sheet AD7193 rev. d | page 49 of 56 50 hz/ 60 hz rejection , sinc 4 filter figure 57 shows the frequency response when f s[9:0] is set to 6 and the post filter averages by 16. this gives an output data rate of 42.10 hz when the master clock equals 4.92 mhz . the sinc filter places the first notch at f notch = f clk /(1024 fs[9:0] ) the postfilter ing places notch es at f notch / avg ( avg is the amount of averaging) and mu ltiples of this frequency ; t her efore, when fs[9:0] is set to 6 and the postfilter averaging is 16, a notch is placed at 800 hz due to the sinc filter and notches are placed at 50 hz and multiples of 5 0 hz due to the postfilter . the notch at 50 hz is a first - order notch ; t herefore, the notch is not wide. this means that the rejection at 50 hz exactly is good, assuming a stable 4.92 mhz master clock. however, in a band of 50 hz 1 hz, the rejection degr ades significantly . the rejection at 50 hz 0.5 hz is 40 db minimum , assuming a stable clock ; t herefore, a good master clock source is recommended when using fast settling mode. 08367-053 ?120 ? 1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 30 60 90 120 150 frequenc y (hz) fi l ter gain (db) figure 57 . filter response for average + decimate filter (sinc 4 f ilter, fs[9:0] = 6 , average by 16) figure 58 shows the filter response when fs[9:0] is set to 5 and the postfilter averages by 1 6 . in this case, the output data rate is equal to 50.53 hz (4.92 mhz master clock) whi le the first filter notch is placed at 60 hz. the rejection at 60 hz 0.5 hz is equal to 4 0 db minimum . 08367-058 ?120 ? 1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 30 60 90 120 150 frequenc y (hz) fi l ter gain (db) figure 58 . filter response for average + decimate filter (sinc 4 f ilt er, fs[9:0] = 5, average by 16) simultaneous 50 hz/60 h z rejection is achieved when fs[9:0] is set to 30 and the postfilter averages by 16. the output data rate is equal to 8.4 hz , wh ereas the rejection at 50 hz 0.5 hz and 60 hz 0.5 hz is typically 44 db. 08367-059 ?120 ? 1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 frequenc y (hz) fi l ter gain (db) 0 30 60 90 120 150 figure 59 . filter respo nse for average + decimate filter (sinc 4 f ilte r, fs[9:0] = 30, average by 16) simultaneous 50 hz and 60 hz rejection is also achieved by using an fs word of 96 and averaging by 16 ; t his places a notch at 50 hz. setting the rej60 bit to 1 plac es a notch at 60 hz (see figure 60) . the output data rate is reduced to 2.63 hz with this configuration but the rejection is improved to typically 100 db at 50 hz 1 hz and 60 hz 1 hz. ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 30 60 90 120 150 frequency (hz) filter gain (db) 08367-157 figure 60 . filter response f or average + decimate filter (sinc 4 filte r, fs[9:0] = 96, average by 16)
AD7193 data sheet rev. d | page 50 of 56 fast settling mode (sinc 3 filter) in fast settling mode, the settling time is close to the inverse of the first filter notch. therefore, the user can achieve 50 hz and/or 60 hz rejection at an output data rate close to 1/50 hz or 1/60 hz. the settling time is equal to 1/output data rate. therefore, the conversion time is constant when converting on a single channel or when converting on several channels. there is no added latency when switching channels. the fast settling mode is enabled using bit avg1 and bit avg0 in the mode register. a postfilter is included after the sinc 4 filter. the postfilter averages by 2, 8, or 16, depending on the settings of the avg1 and avg0 bits. sinc 3 / sinc 4 post filter modulator adc chop 08367-055 figure 61. fast settling mode, sinc 3 filter output data rate and settling time, sinc 3 filter with chop disabled, the output data rate is f adc = f clk /((3 + avg C 1) 1024 fs[9:0] ) f adc is the output data rate. f clk is master clock (4.92 mhz nominal). avg is the average. fs[9:0] is the decimal equivalent of bit fs9 to bit fs0 in the mode register. if avg1 = avg0 = 0, the fast settling mode is not enabled. in this case, the preceding equation is not relevant. the settling time is equal to t settle = 1/ f adc table 35 lists some sample fs words and the corresponding output data rates and settling times. table 35. examples of output data rates and the corresponding settling time (fast settling mode, sinc 3 ) fs[9:0] average output data rate (hz) settling time (ms) 96 16 2.78 360 30 16 8.9 112.5 6 16 44.44 22.5 5 16 53.3 18.75 if the analog input channel is changed, there is no additional delay in generating valid conversions and the device functions as a zero latency adc. channel conversions channel a ch a ch a ch a ch b ch b ch b ch b channel b 1/ f adc ch b ch b 0 8367-056 figure 62. fast settling, sinc 3 filter when the device is converting on a single channel and a step change occurs on the analog input, the adc does not detect the change and continues to output conversions. when the step change is synchronized with the conversion, only fully settled results are output from the adc. however, if the step change is asynchronous to the conversion process, one intermediate result is not completely settled (see figure 63). analog input adc output valid 1/ f adc 0 8367-057 figure 63. step change on analog input, sinc 3 filter 50 hz/60 hz rejection, sinc 3 filter figure 64 shows the frequency response when fs[9:0] is set to 6 and the postfilter averages by 16. this gives an output data rate of 44.44 hz when the master clock is 4.92 mhz. the sinc filter places the first notch at f notch = f clk /(1024 fs[9:0] ) the postfiltering places notches at f notch /avg (avg is the amount of averaging) and multiples of this frequency. therefore, when fs[9:0] is set to 6 and the postfilter averaging is 16, a notch is placed at 800 hz due to the sinc filter and notches are placed at 50 hz and multiples of 50 hz due to the postfilter. the notch at 50 hz is a first-order notch. therefore, the notch is not wide. this means that the rejection at 50 hz exactly is good, assuming a stable 4.92 mhz master clock. however, in a band of 50 hz 1 hz, the rejection degrades significantly. the rejection at 50 hz 0.5 hz is 40 db minimum, assuming a stable clock; there- fore, a good master clock source is recommended when using fast settling mode. 08367-053 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 306090120150 frequency (hz) filter gain (db) figure 64. filter response for average + decimate filter (sinc 3 filter, fs[9:0] = 6, average by 16)
data sheet AD7193 rev. d | page 51 of 56 figure 65 s hows the filter response when fs[9:0] is set to 5 and the pos t f ilter averages by 1 6 . in this case, the output data rate is equal to 5 3 .3 3 hz wh en the first filter notch is placed at 60 hz. the rejection at 60 h z 0.5 hz is equal to 4 0 db minimum . 08367-058 ?120 ?1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 30 60 90 120 150 frequenc y (hz) fi l ter gain (db) figure 65 . filter response for average + decimate filter (sinc 3 f ilt er, fs[9:0] = 5, average by 16) simultaneous 50 hz/60 hz rejection is achieved when fs[9:0] is set to 30 and the postfilt er averages by 16. the output data rate is equal to 8. 9 hz whe reas the rejection at 50 hz 0.5 hz and 60 hz 0.5 hz is typically 4 2 db. 08367-054 ?120 ? 1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 30 60 90 120 150 frequenc y (hz) fi l ter gain (db) figure 66 . filter response for average + decimate filter (sinc 3 f ilter, fs[9:0] = 30 , ave rage by 16) simultaneous 50 hz and 60 hz rejection is also achieved by using an fs word of 96 and averaging by 16 , which places a notch at 50 hz. setting the rej60 bit to 1 places a notch at 60 hz (see figure 67 ). the output data rate is reduced to 2.78 hz with this configuration , but the rejection is improved to 94 db typically at 50 hz 1 hz and 60 hz 1 hz. ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 30 60 90 120 150 frequency (hz) filter gain (db) 08367-164 figure 67 . filter response for average + decimate filter (sinc 3 filte r, fs[9:0] = 96, averag e by 16) fast settling mode ( chop enabled) chop can be enabled in the fast settling mode. with chop enabled, the adc offset and offset drift are minimized. the analog input pins are continuously swapped. with the analog input pins connected in one directio n, the settling time of the sinc filter is allowed and a conversion is recorded. the analog input pins are then inverted, and another settled conversion is obtained. subsequent conversions are averaged so that the offset is minimized. this continuous swapp ing of the analog input pins and the averaging of subsequent conversions means that the offset drift is also minimized. chopping does not change the output data rate. however, the settling time equal s t settle = 2 / f adc conseq uently , if chop is enabled, t he sinc 4 filter is selected, fs[9:0 ] is set to 6 , averaging by 16 is enabled, and the output data rate is equal to 42.1 hz. therefore, the conversion time equals 1/42.10 hz or 23.75 ms , and the settling time is equal to 47.5 ms.
AD7193 data sheet rev. d | page 52 of 56 summary of filter op tions the AD7193 has several filter options. the filter that is chosen affects the output data rate, settling time, the rms noise, and the 50 hz/60 hz rejection. table 36 shows some sample configurations and the corres ponding performance in terms of throughput, settling time , and 50 hz/ 60 hz rejection . table 36 . filter summary 1 filter fs[9:0] output data rate (hz) settling time (ms) throughput 2 (hz) rej60 50 hz rejection (db) 3 sinc 4 , chop d isabled 4 1 4800 0.83 1200 0 no 50 hz or 60 hz rejection sinc 4 , chop disabled 5 960 4.17 240 0 no 50 hz or 60 hz rejection sinc 3 , chop disabled 5 960 3.125 320 0 no 50 hz or 60 hz rejection sinc 4 , chop disabled 480 10 400 2.5 0 120 db ( 50 hz and 60 hz) sinc 3 , chop disabled 480 10 300 3.33 0 100 db (50 hz and 60 hz) sinc 4 , chop disabled 96 50 80 12.5 0 120 db (50 hz only) sinc 4 , chop disabled 96 50 80 12.5 1 8 2 db ( 50 hz and 60 hz) sinc 3 , chop disabled 96 50 60 16.7 0 95 db (50 hz only) sinc 3 , ch op disabled 96 50 60 16.7 1 67 db ( 50 hz and 60 hz) sinc 4 , chop disabled 80 60 66.67 15 0 120 db (60 hz only) sinc 3 , chop disabled 80 60 50 20 0 95 db (60 hz only) sinc 4 , chop disabled, zero latency 96 12.5 80 12.5 0 120 db (50 hz only) sinc 4 , chop di sabled, zero latency 96 12.5 80 12.5 1 8 2 db ( 50 hz and 60 hz) sinc 4 , chop disabled, zero latency 80 15 66.67 15 0 1 2 0 db (60 hz only) sinc 4 , chop enabled 96 12.5 160 6.25 1 80 db (50 hz and 60 hz) sinc 3 , chop enabled 96 16.7 120 8.33 1 67 db (50 hz and 60 hz) fast settling (sinc 4 , chop disabled, average by 16) 96 2.63 380 2.63 1 100 db (50 hz and 60 hz) fast settling (sinc 4 , chop disabled, average by 16) 96 2.78 360 2.78 1 94 db (50 hz and 60 hz) fast settling (sinc 4 , chop disabled, average by 16 ) 5 50.53 19.79 50.53 0 4 0 db (60 hz only) fast settling (sinc 3 , chop disabled, average by 16) 5 53.33 18.75 53.33 0 4 0 db (60 hz only) fast settling (sinc 4 , chop disabled, average by 16) 6 42.10 23.75 42.1 0 40 db (50 hz only) fast settling (sinc 3 , c hop disabled, average by 16) 6 44.44 22.5 44.44 0 40 db (50 hz o nly) 1 these calculations assume a 4.92 mhz stable master clock. 2 throughput is the rate at which conversions are available when several channels are enabled. in zero latency mode, the output data rate and throughput are equal. 3 for fast settling mode, the 50 hz/60 hz rejection is measured in a band of 0.5 hz around 50 hz and/or 60 hz. for all other m odes, a region of 1 hz around 50 hz and/or 60 hz is used. 4 for output dates rates greater than 1 khz, the sinc 4 filter is recomm ended.
data sheet AD7193 rev. d | page 53 of 56 grounding and layout because the analog inputs and reference inputs are differential, most of the voltages in the analog modulator are common - mode voltages. the high common - mode rej ection of the part remove s common - mode noise on these inputs. the analog and digital supplies to the AD7193 are independent and separately pinned out to minimize coupling between the analog and digital sections of the device. the digital filter provide s re jection of broadband noise on the power supplies, except at integer multiples of the modulator sampling frequency. connect an rc filter to each analog input pin to provide rejection at the modula tor sampling frequency. a 100 resistor in series with each analog input , a 0.1 f capacitor between the analog input pins, and a 0.01 f capacitor from each analog input to agnd are advised. the digital filter also removes noise from the analog and refe rence inputs provided that these noise sources do not saturate the analog modulator. as a result, the AD7193 is more immune to noise interf erence than a conventional high resolution converter. however, because the resolution of the AD7193 is so high and t he noise levels from the converter so low, care must be taken with regard to grounding and layout. the printed circuit board (pcb) that houses the adc must be designed so that the analog and digital sections are separated and confined to certain areas of t he board. this facilitates the use of ground planes that can be easily separated. a minimum etch technique is generally best for ground planes because it gives the best shielding. although the AD7193 has separate pins for analog and digital ground, the agn d and dgnd pins are tied together internally via the substrate. therefore, the user must not tie these two pins t o separate ground planes unless the ground planes are connected together near the AD7193 . in systems in which the agnd and dgnd are connected some - where else in the system (that is , the power supply of the system ) , they should not be connected again at the AD7193 because a ground loop result s . in these situations , it is recommended that the ground pins of the AD7193 be tied to the agnd plane. i n any layout , the user must keep in mind the flow of currents in the system, ensuring that the paths for all currents are as close as possible to the p aths the currents took to reach their destinations . avoid forcing digital currents to flow through the ag nd. avoid running digital lines under the device because this couple s noise onto the die and allow s t he analo g ground plane to run under the AD7193 to prevent noise coupling. the power supply lines to the AD7193 must use as wide a trace as possible to prov ide low impedance paths and reduce the effects of glitches on th e power supply line. shield fast switching signals like clocks with digital ground to prevent radiating noise to other sections of the board and never run clock signals near the analog inputs. avoid crossover of digital and analog signals. run t races on opposite sides of the board at right angles to each other. this reduce s the effects of feedthrough through the board. a microstrip technique is by far the best but is not always possible with a double - sided board. in this technique, the component side of the boar d is dedicated to ground planes, whereas signals are placed on the solder side. good decoupling is important when using high resolution adcs. decouple a ll analog supplies with 10 f tanta lum capacitors in parallel with 0.1 f capacitors to agnd. to achieve the best results from these decoupling components, place them as close as possible to the device, ideally right up against the device. decouple a ll logic chips with 0.1 f ceramic capaci tors to dgnd. in systems in which a common supply voltage is used to drive both the av dd and dv dd of the AD7193 , it is recommended that the system av dd supply be used. for this supply , place the recommended analog supply decoupling capacitors between the a v dd pin of the AD7193 and agnd and the recommended digital supply decoupling capacitor between the dv dd pin of the AD7193 and dgnd.
AD7193 data sheet rev. d | page 54 of 56 applications informa tion the AD7193 provides a low cost, high resolution analog - to - digital function . because the analog - t o - digital function is provided by a - ? architecture, the part is more immune to noisy environments, making it ideal for use in sensor measurement and industrial and process control applications. f low m eter figure 68 shows the AD7193 being used in a flowmeter applica tion t hat consists of two pressure transducers with the rate of flow being equal to the pressure difference. the pressure transducers are arranged in a bridge network and give a differential output voltage between its out+ and out ? terminals. with rated fu ll- scale pressure (in this case 300 mmhg) on the transducer, the differential output voltage is 3 mv/v of the input voltage (that is, the voltage between the in+ and in C terminals). assuming a 5 v excitation voltage, the full - scale output range from the tr ansducer is 15 mv. the excitation voltage for the bridge can be used to directly provide the reference for the adc, because the reference input range includes the supply voltage. a second advantage of using the AD7193 in transducer - based applications is th at the bridge power - down switch can be fully utilized in low power applications. the bridge power - down switch is connected in series with the cold side of the bridges. in normal operation, the switch is closed and measurements are taken. in applications w here power is of concern, the AD7193 can be placed in power - down mode, thus significantly reducing the power consumed in the application. in addition, the bridge powe r - down switch can be opened while the AD7193 is in power - down mode, thus avoiding unneces sary power consumption by the front - end transducers. when the parts are taken out of power - down mode and the bridge power - down switch is closed, the us er should ensure that the front - end circuitry is fully settled before attempting a read from the AD7193. in figure 68 , temperature compensation is performed using a thermistor. in addition, the reference voltage for the temperature measurement is derived from a precision resistor in series with the thermistor. this allows a ratiomet ric measurement so that variation of the excitation voltage has no affect on the measurement ( it is the ra tio of the precision reference resistance to the thermistor resistance that is measured) for simplicity, external filters are not shown in figure 68 ; h owever, an rc antialias filter must be included on each analog input. this is required because the on - chip digital filter does not provide any rejection around the modulator sampling frequency or multiples of this frequency. suitable values are a 100 resi stor in series with each analog input, a 0.1 f capacitor between the analog input pins , and a 0.01 f capacitor from each analog input pin to agnd. mclk1 mclk2 refin2(+) refin2(?) dv dd dgnd 5v ain1 in+ in? out? out+ ain2 ain3 ain4 refin1(?) bpdsw agnd AD7193 refin1(+) reference detect serial interface and control logic clock circuitry av dd agnd dout/rdy din sclk cs sync av dd agnd ain5 ain6 in+ in? out? out+ - adc pga mux 08367-064 figure 68 . typical application (flo wmeter )
data sheet AD7193 rev. d | page 55 of 56 outline dimensions compliant to jedec standards mo-153-ae 28 15 14 1 8 0 seating plane c oplanarit y 0.10 1.20 max 6.40 bsc 0.65 bsc pin 1 0.30 0.19 0.20 0.09 4.50 4.40 4.30 0.75 0.60 0.45 9.80 9.70 9.60 0.15 0.05 figure 69. 28-lead thin shrink small outline package [tssop] (ru-28) dimensions shown in millimeters compliant to jedec standards mo-220-whhd. 1 0.50 bsc 3.50 ref bottom view top view pin 1 indicator 32 9 16 17 24 25 8 exposed pad p i n 1 i n d i c a t o r 3.65 3.50 sq 3.45 s eating plane 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.25 0.18 5.10 5.00 sq 4.90 0.80 0.75 0.70 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.50 0.40 0.30 0.25 min 04-02-2012-a figure 70. 32-lead lead frame chip scale package [lfcsp_wq] 5 mm 5 mm body, very, very thin quad (cp-32-11) dimensions shown in millimeters ordering guide model 1 temperature range package description package option AD7193bruz ?40c to +105c 28-lead tssop ru-28 AD7193bruz-reel ?40c to +105 c 28-lead tssop ru-28 AD7193bcpz ?40c to +105c 32-lead lfcsp_wq cp-32-11 AD7193bcpz-rl ?40c to +105c 32-lead lfcsp_wq cp-32-11 AD7193bcpz-rl7 ?40c to +105c 32-lead lfcsp_wq cp-32-11 eval-AD7193ebz evaluation board 1 z = rohs compliant part.
AD7193 data sheet rev. d | page 56 of 56 notes ? 2009 C 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d08367 - 0- 3/13(d)

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